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參數資料
| 型號： | 514DCAXXXXXXBAG |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | XO, clock |
| 英文描述： | 250 MHz, OTHER CLOCK GENERATOR, PDSO6 |
| 封裝： | 3.20 X 5 MM, ROHS COMPLIANT PACKAGE-6 |
| 文件頁數： | 1/32頁 |
| 文件大小： | 267K |
| 代理商： | 514DCAXXXXXXBAG |
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Preliminary Rev. 0.9 3/11
Copyright 2011 by Silicon Laboratories
Si514
A NY-F REQUENCY I 2C P ROGRAMMABLE XO (100 kH Z TO 250 M H Z)
Features
Applications
Description
The Si514 user-programmable I2C XO utilizes Silicon Laboratories' advanced PLL
technology to provide any frequency from 100 kHz to 250 MHz with programming
resolution of 0.026 parts per billion. The Si514 uses a single integrated crystal and
Silicon Labs’ proprietary DSPLL synthesizer to generate any frequency across this
range using simple I2C commands. Ultra-fine tuning resolution replaces DACs and
VCXOs with an all-digital PLL solution that improves performance where
synchronization is necessary or in free-running reference clock applications. This
solution provides superior supply noise rejection, simplifying low jitter clock
generation in noisy environments. Crystal ESR and DLD are individually
production-tested to guarantee performance and enhance reliability.
The Si514 is factory-configurable for a wide variety of user specifications, including
startup frequency, I2C address, supply voltage, output format, and stability. Specific
configurations are factory-programmed at time of shipment, eliminating long lead
times and non-recurring engineering charges associated with custom frequency
oscillators.
Functional Block Diagram
Programmable to any frequency
from 100 kHz to 250 MHz
0.026 ppb frequency tuning
resolution
Glitch suppression on OE, power
on and frequency transitions
1 ps phase jitter (rms, max)
2- to 4-week lead times
Total stability includes 10-year
aging
Comprehensive production test
coverage includes crystal ESR and
DLD
On-chip LDO for power supply
noise filtering
3.3, 2.5, or 1.8 V operation
Differential (LVPECL, LVDS,
HCSL) or CMOS output options
Optional integrated 1:2 CMOS
fanout buffer
Industry standard 5 x 7 and
3.2x 5mm packages
–40 to 85 oC operation
All-digital PLLs
DAC+ VCXO replacement
SONET/SDH/OTN
3G-SDI/HD-SDI/SDI
Datacom
Industrial automation
FPGA/ASIC clock generation
FPGA synchronization
Ordering Information:
See page 25.
Pin Assignments:
See page 24.
Si5602
1
2
3
6
5
4
GND
SCL
VDD
CLK+
CLK–
SDA
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