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參數資料
| 型號： | 74F632 |
| 英文描述： | 32-Bit Parallel Error Detection and Correction Circuit |
| 中文描述： | 32位并行錯誤檢測和校正電路 |
| 文件頁數： | 1/14頁 |
| 文件大?。?/td> | 225K |
| 代理商： | 74F632 |
TL/F/9579
D
May 1991
DP8406 (54F/74F632)
32-Bit Parallel Error Detection and Correction Circuit
General Description
The DP8406 device is a 32-bit parallel error detection and
correction circuit (EDAC) in a 52-pin or 68-pin package. The
EDAC uses a modified Hamming code to generate a 7-bit
check word from a 32-bit data word. This check word is
stored along with the data word during the memory write
cycle. During the memory read cycle, the 39-bit words from
memory are processed by the EDAC to determine if errors
have occurred in memory.
Single-bit errors in the 32-bit data word are flagged and cor-
rected.
Single-bit errors in the 7-bit check word are flagged, and the
CPU sends the EDAC through the correction cycle even
though the 32-bit data word is not in error. The correction
cycle will simply pass along the original 32-bit data word in
this case and produce error syndrome bits to pinpoint the
error-generating location.
Dual-bit errors are flagged but not corrected. These errors
may occur in any two bits of the 39-bit word from memory
(two errors in the 32-bit data word, two errors in the 7-bit
check word, or one error in each word). The gross-error
condition of all LOWs or all HIGHs from memory will be
detected. Otherwise, errors in three or more bits of the
39-bit word are beyond the capabilities of these devices to
detect.
Read-modify-write (byte-control) operations can be per-
formed by using output latch enable, LEDBO, and the indi-
vidual OEB
0
through OEB
3
byte control pins.
Diagnostics are performed on the EDACs by controls and
internal paths that allow the user to read the contents of the
Data Bit and Check Bit input latches. These will determine if
the failure occurred in memory or in the EDAC.
Features
Y
Detects and corrects single-bit errors
Y
Detects and flags dual-bit errors
Y
Built-in diagnostic capability
Y
Fast write and read cycle processing times
Y
Byte-write capability
Y
Guaranteed 4000V minimum ESD protection
pin
and
function
SN74ALS632A thru SN74ALS635 series
Y
Fully
compatible
with
TI’s
Simplified Functional Block
TL/F/9579–9
Device
Package
Byte-Write
Output
DP8406
52-Pin
yes
TRI-STATE
é
TRI-STATE
é
DP8406
68-Pin
yes
FAST
é
and TRI-STATE
é
are registered trademarks of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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PDF描述 |
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| 54F632 | 32-Bit Parallel Error Detection and Correction Circuit |
| 54F632DM | Error Detection & Correction (EDAC) |
| 54F632DMQB | Error Detection & Correction (EDAC) |
| 54F632DMQR | Error Detection & Correction (EDAC) |
| 54F632LM | Error Detection & Correction (EDAC) |
相關代理商/技術參數 |
參數描述 |
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| 74F632QC | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:32-Bit Parallel Error Detection and Correction Circuit |
| 74F632VC | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:32-Bit Parallel Error Detection and Correction Circuit |
| 74F64 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:4-2-3-2-Input AND-OR-Invert Gate |
| 74F64 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| 74F640 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Octal Bus Transceiver with 3-STATE Outputs |
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