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參數資料
| 型號： | A1356LKB-T |
| 廠商： | Allegro Microsystems Inc |
| 文件頁數： | 8/20頁 |
| 文件大小： | 432K |
| 描述： | IC SENSOR HALL EFFECT 3 SIP |
| 標準包裝： | 4,000 |
| 傳感范圍： | 45m%D/G ~ 75m%D/G |
| 類型： | 線性 - 可編程 |
| 電源電壓： | 4.5 V ~ 18 V |
| 電流 - 電源： | 10mA |
| 電流 - 輸出（最大）： | 25mA |
| 輸出類型： | 數字式， PWM 編碼 |
| 特點： | 高精度 |
| 工作溫度： | -40°C ~ 150°C |
| 封裝/外殼： | 3-SIP |
| 供應商設備封裝： | 3-SIP |
| 包裝： | 散裝 |
| 其它名稱： | 620-1369 A1356LK-T |
High Precision Linear Hall-Effect Sensor IC
With an Open Drain Pulse Width Modulated Output
A1356
8
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Characteristic Definitions
Power-On Time When the supply is ramped to its operating
voltage, the device requires a finite time to power its internal
components before supplying a valid PWM output duty-cycle.
Power-On Time, t
PO
, is defined as the time it takes for the output
voltage to settle within ?0% of its steady state value after the
power supply has reached its minimum specified operating volt-
age, V
CC
(min). (See figure 1.)
Propagation Delay Traveling time of signal from input Hall
plate to output stage of device. (See figure 2.)
Response Time The time interval between a) when the applied
magnetic field reaches 90% of its final value, and b) when the
sensor IC reaches 90% of its output corresponding to the applied
magnetic field. (See figure 2.)
PWM Rise Time The time elapsed between 10% and 90% of
the rising signal value when output switches from low to high
states.
PWM Fall Time The time elapsed between 90% and 10% of the
falling signal value when output switches from high to low states.
Quiescent Duty Cycle In the quiescent state (no significant
magnetic field: B = 0 G), the output duty cycle, D
(Q)
, equals a
specific programmed duty cycle throughout the entire operating
ranges of V
CC
and ambient temperature, T
A
.
Guaranteed Quiescent Duty Cycle Output Range The
Quiescent Duty Cycle Output, D
(Q)
, can be programmed around
its nominal value of 50% D, within the Guaranteed Quiescent
Duty Cycle Range limits: D
(Q)
(min) and D
(Q)
(max). The available
guaranteed programming range for D
(Q)
falls within the distribu-
tions of the minimum and the maximum programming code for
setting D
(Q)
. (See figure 3.)
Average Quiescent Duty Cycle Output Step Size The
average quiescent duty cycle output step size for a single device
is determined using the following calculation:
D
(Q)
(max)
D
(Q)
(min)
2
n
1
Step
D(Q)
=
,
(1)
where:
n is the number of available programming bits in the trim range,
2
n
1 is the value of programming steps in the range,
D
(Q)
(max) is the maximum reached quiescent duty cycle, and
D
(Q)
(min) is minimum reached quiescent duty cycle.
Figure 1. Definition of Power-On Time
Figure 2. Definitions of Propagation Delay and Response Time
Figure 3. Definition of Guaranteed Quiescent Voltage Output Range
Guaranteed D
(Q)
Programming
Range
D
(Q)
(min)
D
(Q)
(max)
Max Code D
(Q)
Distribution
Min Code D
(Q)
Distribution
Initial D
(Q)
Distribution
Propagation
Delay
0.5 ms
Output
Time
Applied Magnetic
Field, B
Response
Time
Time
V+
V
CC
(min)
t
PO
First valid duty cycle
V
CC
A1356
Output
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