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參數資料
| 型號： | AD7675 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 100 kSPS, Differential ADC |
| 中文描述： | 16位，100 kSPS的，差分ADC |
| 文件頁數： | 14/20頁 |
| 文件大小： | 399K |
| 代理商： | AD7675 |
REV. 0
AD7675
–
14
–
t
9
RESET
DATA
BUSY
CNVST
t
8
Figure 12. RESET Timing
For other applications, conversions can be automatically initi-
ated. If
CNVST
is held low when BUSY is low, the AD7675
controls the acquisition phase and then automatically initiates a
new conversion. By keeping
CNVST
low, the AD7675 keeps
the conversion process running by itself. It should be noted that
the analog input has to be settled when BUSY goes low. Also, at
power-up,
CNVST
should be brought low once to initiate the
conversion process. In this mode, the AD7675 could sometimes
run slightly faster than the guaranteed limit of 100 kSPS.
DIGITAL INTERFACE
The AD7675 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7675 digital interface also accommodates both 3 V or 5 V
logic by simply connecting the OVDD supply pin of the AD7675
to the host system interface digital supply. Finally, by using the
OB/
2C
input pin, either two’s complement or straight binary
coding can be used.
The two signals
CS
and
RD
control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually,
CS
allows the selection of each AD7675 in
multicircuits applications and is held low in a single AD7675
design.
RD
is generally used to enable the conversion result on
the data bus.
CNVST
BUSY
DATA
BUS
CS
=
RD
= 0
PREVIOUS CONVERSION DATA
NEW DATA
t
1
t
10
t
4
t
3
t
11
Figure 13. Master Parallel Data Timing for Reading
(Continuous Read)
PARALLEL INTERFACE
The AD7675 is configured to use the parallel interface (Figure 13)
when the SER/
PAR
is held low. The data can be read either
after each conversion, which is during the next acquisition
phase, or during the following conversion as shown, respectively,
in Figure 14 and Figure 15. When the data is read during the
conversion, however, it is recommended that it be read-only
during the first half of the conversion phase. That avoids any
potential feedthrough between voltage transients on the digital
interface and the most critical analog conversion circuitry.
DATA
BUS
t
12
t
13
BUSY
CS
RD
CURRENT
CONVERSION
Figure 14. Slave Parallel Data Timing for Reading
(Read after Convert)
CS
= 0
CNVST,
RD
t
1
PREVIOUS
CONVERSION
DATA
BUS
t
12
t
13
BUSY
t
4
t
3
Figure 15. Slave Parallel Data Timing for Reading (Read
During Convert)
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 16, the LSB byte is output on D[7:0] and
the MSB is output on D[15:8] when BYTESWAP is low. When
BYTESWAP is high, the LSB and MSB bytes are swapped and
the LSB is output on D[15:8] and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16-bit data
can be read in two bytes on either D[15:8] or D[7:0].
CS
RD
BYTE
PINS D[15:8]
PINS D[7:0]
HI-Z
HI-Z
HIGH BYTE
LOW BYTE
LOW BYTE
HIGH BYTE
HI-Z
HI-Z
t
12
t
12
t
13
Figure 16. 8-Bit Parallel Interface
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