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參數資料
| 型號： | AD7675 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 100 kSPS, Differential ADC |
| 中文描述： | 16位，100 kSPS的，差分ADC |
| 文件頁數： | 4/20頁 |
| 文件大小： | 399K |
| 代理商： | AD7675 |
REV. 0
AD7675
–4–
Table I. Serial Clock Timings in Master Read after Convert
DIVSCLK[1]
DIVSCLK[0]
0
0
0
1
1
0
1
1
Unit
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Typical
Internal SCLK HIGH Minimum
Internal SCLK LOW Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
Busy High Width Maximum
t
18
t
19
t
19
t
20
t
21
t
22
t
23
t
24
t
28
3
25
40
12
7
4
2
3
2
17
50
70
22
21
18
4
60
2.5
17
100
140
50
49
18
30
140
3.5
17
200
280
100
99
18
89
300
5.75
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
ABSOLUTE MAXIMUM RATINGS
1
Analog Inputs
IN+
2
, IN–
2
, REF, REFGND . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . .
±
0.3 V
Supply Voltages
AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
AVDD to DVDD,
AVDD to OVDD . . . . . . . . . . . . . .
±
7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
7 V
Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
Internal Power Dissipation
3
. . . . . . . . . . . . . . . . . . . . 700 mW
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150
°
C
Storage Temperature Range . . . . . . . . . . . . –65
°
C to +150
°
C
Lead Temperature Range
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300
°
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
See Analog Input section.
3
Specification is for device in free air: 48-Lead LQFP:
JA
= 91
°
C/W,
JC
= 30
°
C/W.
TO OUTPUT
PIN
C
L
60pF
1
500 A
I
OH
1.6mA
I
OL
1.4V
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
1
Figure 1. Load Circuit for Digital Interface Timing, SDOUT,
SYNC, SCLK Outputs, C
L
= 10 pF
0.8V
2V
2V
0.8V
t
DELAY
2V
0.8V
t
DELAY
Figure 2. Voltage Reference Levels for Timing
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7675 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Package
Option
Model
Temperature Range
–40
°
C to +85
°
C
–40
°
C to +85
°
C
Package Description
AD7675AST
AD7675ASTRL
EVAL-AD7675CB
1
EVAL-CONTROL BRD2
2
Quad Flatpack (LQFP)
Quad Flatpack (LQFP)
Evaluation Board
Controller Board
ST-48
ST-48
NOTES
1
This board can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/
demonstration purposes.
2
This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
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