欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: AD7675AST
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 16-Bit, 100 kSPS, Differential ADC
中文描述: 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48
封裝: 1.40 MM HEIGHT, PLASTIC, MS-026BBC, LQFP-48
文件頁數: 13/20頁
文件大小: 399K
代理商: AD7675AST
REV. 0
AD7675
13
Care should also be taken with the reference temperature coeffi-
cient of the voltage reference which directly affects the full-scale
accuracy if this parameter matters. For instance, a
±
15 ppm/
°
C
tempco of the reference changes the full scale by
±
1 LSB/
°
C.
V
REF
, as mentioned in the specification table, could be increased
to AVDD – 1.85 V. The benefit here is the increased SNR
obtained as a result of this increase. Since the input range is
defined in terms of V
REF
, this would essentially increase the
range to make it a
±
3 V input range with an AVDD above
4.85 V. The theoretical improvement as a result of this increase
in reference is 1.58 dB (20 log [3/2.5]). Due to the theoretical
quantization noise, however, the observed improvement is
approximately 1 dB. The AD780 can be selected with a 3 V
reference voltage.
Power Supply
The AD7675 uses three sets of power supply pins: an analog
5 V supply AVDD, a digital 5 V core supply DVDD, and a
digital input/output interface supply OVDD. The OVDD supply
allows direct interface with any logic working between 2.7 V and
5.25 V. To reduce the number of supplies needed, the digital
core (DVDD) can be supplied through a simple RC filter from
the analog supply as shown in Figure 5. The AD7675 is inde-
pendent of power supply sequencing and thus free from supply
voltage induced latchup. Additionally, it is very insensitive to
power supply variations over a wide frequency range as shown
in Figure 9.
FREQUENCY
Hz
75
P
35
65
10k
10M
1k
1M
55
100k
45
70
60
50
40
Figure 9. PSRR vs. Frequency
POWER DISSIPATION
The AD7675 automatically reduces its power consumption at
the end of each conversion phase. During the acquisition phase,
the operating currents are very low which allows a significant
power saving when the conversion rate is reduced as shown in
Figure 10. This feature makes the AD7675 ideal for very low-
power battery applications.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, the digital inputs need to be driven
close to the power rails (i.e., DVDD and DGND) and OVDD
should not exceed DVDD by more than 0.3 V.
SAMPLING RATE
SPS
P
0.1
10k
100
100k
10
10k
100
1k
1
100k
1k
10
1M
Figure 10. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
Figure 11 shows the detailed timing diagrams of the conversion
process. The AD7675 is controlled by the signal
CNVST
which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conver-
sion is complete. The
CNVST
signal operates independently of
CS
and
RD
signals.
CNVST
t
1
t
2
MODE
ACQUIRE
CONVERT
ACQUIRE
CONVERT
t
7
t
8
BUSY
t
4
t
3
t
5
t
6
Figure 11. Basic Conversion Timing
For true sampling applications, the recommended operation of
the
CNVST
signal is as follows:
CNVST
must be held high from the previous falling edge of
BUSY, and during a minimum delay corresponding to the
acquisition time t
8
; then, when
CNVST
is brought low, a
conversion is initiated and BUSY signal goes high until the
completion of the conversion. Although
CNVST
is a digital
signal, it should be designed with this special care with fast,
clean edges and levels, with minimum overshoot and under-
shoot or ringing.
For applications where the SNR is critical, the
CNVST
signal should
have a very low jitter. Some solutions to achieve that are to use a
dedicated oscillator for
CNVST
generation or, at least, to clock
it with a high-frequency low-jitter clock, as shown in Figure 5.
相關PDF資料
PDF描述
AD7675ASTRL 16-Bit, 100 kSPS, Differential ADC
AD7676 16-Bit +-1 LSB INL, 500 kSPS, Differential ADC
AD7676AST 16-Bit +-1 LSB INL, 500 kSPS, Differential ADC
AD7676ASTRL 16-Bit +-1 LSB INL, 500 kSPS, Differential ADC
AD7677 16-Bit, 1 LSB INL, 1 MSPS Differential ADC
相關代理商/技術參數
參數描述
AD7675ASTRL 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 16-bit Parallel/Serial 48-Pin LQFP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 100KSPS 16BIT PARALLEL/SERL 48LQFP - Tape and Reel
AD7675ASTZ 功能描述:IC ADC 16BIT DIFF INP 48LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數:12 采樣率(每秒):20M 數據接口:并聯 轉換器數目:2 功率耗散(最大):155mW 電壓電源:模擬和數字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP(7x7) 包裝:Digi-Reel® 輸入數目和類型:4 個單端,單極;2 個差分,單極 產品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6
AD7675ASTZRL 功能描述:IC ADC 16BIT DIFF INP 48LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 標準包裝:1,000 系列:- 位數:12 采樣率(每秒):300k 數據接口:并聯 轉換器數目:1 功率耗散(最大):75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC(0.295",7.50mm 寬) 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端,單極;1 個單端,雙極
AD7676 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit +-1 LSB INL, 500 kSPS, Differential ADC
AD7676ACP 制造商:Analog Devices 功能描述:ADC SGL SAR 500KSPS 16BIT PARALLEL/SERL 48LFCSP - Trays
主站蜘蛛池模板: 新河县| 广州市| 德惠市| 河北区| 沾化县| 闵行区| 海门市| 赞皇县| 富源县| 响水县| 白沙| 邓州市| 于都县| 永寿县| 平舆县| 高台县| 迁安市| 淳安县| 商城县| 通江县| 太保市| 肇东市| 沂水县| 将乐县| 中山市| 雅安市| 宁陕县| 革吉县| 河东区| 玉溪市| 永安市| 大石桥市| 丰城市| 深州市| 山丹县| 邓州市| 大厂| 湖南省| 崇文区| 泌阳县| 昌江|