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參數(shù)資料
| 型號： | AD7675AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 100 kSPS, Differential ADC |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | 1.40 MM HEIGHT, PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 399K |
| 代理商： | AD7675AST |
REV. 0
AD7675
–
15
–
t
3
BUSY
CS
,
RD
CNVST
SYNC
SCLK
SDOUT
1
2
3
14
15
16
D15
D14
D2
D1
D0
X
EXT/
INT
= 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t
14
t
20
t
15
t
16
t
22
t
23
t
29
t
28
t
18
t
19
t
21
t
30
t
25
t
24
t
26
t
27
Figure 17. Master Serial Data Timing for Reading (Read after Convert)
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
D15
D14
D2
D1
D0
X
1
2
3
14
15
16
t
18
BUSY
SYNC
SCLK
SDOUT
CS
,
RD
CNVST
t
3
t
1
t
17
t
14
t
15
t
19
t
20
t
21
t
16
t
22
t
23
t
24
t
27
t
26
t
25
EXT/
INT
= 0
Figure 18. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
SERIAL INTERFACE
The AD7675 is configured to use the serial interface when the
SER/
PAR
is held high. The AD7675 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin.
MASTER SERIAL INTERFACE
Internal Clock
The AD7675 is configured to generate and provide the serial
data clock SCLK when the EXT/
INT
pin is held low. The AD7675
also generates a SYNC signal to indicate to the host when the
serial data is valid. The serial clock SCLK and the SYNC signal
can be inverted if desired. The output data is valid on both the
rising and falling edge of the data clock. Depending on RDC/
SDIN input, the data can be read after each conversion, or
during the following conversion. Figure 17 and Figure 18 show
the detailed timing diagrams of these two modes.
Usually, because the AD7675 has a longer acquisition phase
than the conversion phase, the data is read immediately after
conversion. That makes the mode master, read after conversion,
the most recommended serial mode when it can be used.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7675ASTRL | 16-Bit, 100 kSPS, Differential ADC |
| AD7676 | 16-Bit +-1 LSB INL, 500 kSPS, Differential ADC |
| AD7676AST | 16-Bit +-1 LSB INL, 500 kSPS, Differential ADC |
| AD7676ASTRL | 16-Bit +-1 LSB INL, 500 kSPS, Differential ADC |
| AD7677 | 16-Bit, 1 LSB INL, 1 MSPS Differential ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7675ASTRL | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 16-bit Parallel/Serial 48-Pin LQFP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 100KSPS 16BIT PARALLEL/SERL 48LQFP - Tape and Reel |
| AD7675ASTZ | 功能描述:IC ADC 16BIT DIFF INP 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7675ASTZRL | 功能描述:IC ADC 16BIT DIFF INP 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7676 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit +-1 LSB INL, 500 kSPS, Differential ADC |
| AD7676ACP | 制造商:Analog Devices 功能描述:ADC SGL SAR 500KSPS 16BIT PARALLEL/SERL 48LFCSP - Trays |
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