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參數資料
型號: AD7676AST
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 16-Bit +-1 LSB INL, 500 kSPS, Differential ADC
中文描述: 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48
封裝: 1.40 MM HEIGHT, PLASTIC, MS-026BBC, LQFP-48
文件頁數: 16/20頁
文件大?。?/td> 321K
代理商: AD7676AST
REV. 0
AD7676
16
In read-after-conversion mode, it should be noted that, unlike in
other modes, the signal BUSY returns low after the 16 data bits
are pulsed out and not at the end of the conversion phase which
results in a longer BUSY width.
In read-during-conversion mode, the serial clock and data toggle
at appropriate instances, which minimizes potential feedthrough
between digital activity and the critical conversion decisions.
SLAVE SERIAL INTERFACE
External Clock
The AD7676 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/
INT
pin is
held high. In this mode, several methods can be used to read the
data. The external serial clock is gated by
CS
and the data are
output when both
CS
and
RD
are low. Thus, depending on
CS
, the data can be read after each conversion or during the
following conversion. The external clock can be either a con-
tinuous or discontinuous clock. A discontinuous clock can be
either normally high or normally low when inactive. Figure 19
and Figure 20 show the detailed timing diagrams of these meth-
ods. Usually, because the AD7676 has a longer acquisition
phase than the conversion phase, the data are read immediately
after conversion.
While the AD7676 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is particu-
larly important during the second half of the conversion phase
because the AD7676 provides error correction circuitry that can
correct for an improper bit decision made during the first half of
the conversion phase. For this reason, it is recommended that when
an external clock is being provided, it is a discontinuous clock
that is toggling only when BUSY is low or, more importantly,
that it does not transition during the latter half of BUSY high.
External Discontinuous Clock Data Read after Conversion
This mode is the most recommended of the serial slave modes.
Figure 19 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
low, the result of this conversion can be read while both
CS
and
RD
are low. The data is shifted out, MSB first, with 16 clock
pulses and is valid on both rising and falling edge of the clock.
Among the advantages of this method, the conversion perfor-
mance is not degraded because there is no voltage transients on
the digital interface during the conversion process.
Another advantage is to be able to read the data at any speed up
to 40 MHz, which accommodates both slow digital host inter-
face and the fastest serial reading.
Finally, in this mode only, the AD7676 provides a “daisy chain”
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing compo-
nent count and wiring connections when it is desired as it is, for
instance, in isolated multiconverters applications.
An example of the concatenation of two devices is shown in
Figure 21. Simultaneous sampling is possible by using a com-
mon CNVST signal. It should be noted that the RDC/SDIN
input is latched on the opposite edge of SCLK of the one used
to shift out the data on SDOUT. Hence, the MSB of the
“upstream” converter just follows the LSB of the “downstream”
converter on the next SCLK cycle.
CS
SCLK
SDOUT
D15
D14
D1
D0
D13
X15
X14
X13
X1
X0
Y15
Y14
BUSY
SDIN
INVSCLK = 0
X15
X14
X
1
2
3
14
15
16
17
18
EXT/
INT
= 1
RD
= 0
t
35
t
36
t
37
t
31
t
32
t
34
t
16
t
33
Figure 19. Slave Serial Data Timing for Reading (Read after Convert)
相關PDF資料
PDF描述
AD7676ASTRL 16-Bit +-1 LSB INL, 500 kSPS, Differential ADC
AD7677 16-Bit, 1 LSB INL, 1 MSPS Differential ADC
AD7677AST 16-Bit, 1 LSB INL, 1 MSPS Differential ADC
AD7677ASTRL 16-Bit, 1 LSB INL, 1 MSPS Differential ADC
AD7679CB1 18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC
相關代理商/技術參數
參數描述
AD7676ASTRL 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Parallel/Serial 48-Pin LQFP T/R
AD7676ASTZ 功能描述:IC ADC 16BIT 500KSPS DIFF 48LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 標準包裝:1 系列:microPOWER™ 位數:8 采樣率(每秒):1M 數據接口:串行,SPI? 轉換器數目:1 功率耗散(最大):- 電壓電源:模擬和數字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤(4x4) 包裝:Digi-Reel® 輸入數目和類型:8 個單端,單極 產品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6
AD7676ASTZKL1 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD7676ASTZRL 功能描述:IC ADC 16BIT DIFF INP 48LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 標準包裝:1 系列:- 位數:14 采樣率(每秒):83k 數據接口:串行,并聯 轉換器數目:1 功率耗散(最大):95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP(0.600",15.24mm) 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端,雙極
AD7677 制造商:AD 制造商全稱:Analog Devices 功能描述:18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC
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