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參數資料
| 型號： | AD7677 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 1 LSB INL, 1 MSPS Differential ADC |
| 中文描述： | 16位，1 LSB INL和1 MSPS的差分ADC |
| 文件頁數： | 16/20頁 |
| 文件大?。?/td> | 322K |
| 代理商： | AD7677 |
REV. 0
AD7677
–16–
CS
RD
BYTE
PINS D[15:8]
PINS D[7:0]
HI-Z
HI-Z
HIGH BYTE
LOW BYTE
LOW BYTE
HIGH BYTE
HI-Z
HI-Z
t
12
t
12
t
13
Figure 16. 8-Bit Parallel Interface
SERIAL INTERFACE
The AD7677 is configured to use the serial interface when the
SER/PAR is held high. The AD7677 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin.
MASTER SERIAL INTERFACE
Internal Clock
The AD7677 is configured to generate and provide the serial
data clock SCLK when the EXT/
INT
pin is held low. The AD7677
also generates a SYNC signal to indicate to the host when the
serial data is valid. The serial clock SCLK and the SYNC signal
can be inverted if desired. The output data is valid on both the
t
3
BUSY
CS
,
RD
CNVST
SYNC
SCLK
SDOUT
1
2
3
14
15
16
D15
D14
D2
D1
D0
X
EXT/
INT
= 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t
14
t
20
t
15
t
16
t
22
t
23
t
29
t
28
t
18
t
19
t
21
t
30
t
25
t
24
t
26
t
27
Figure 17. Master Serial Data Timing for Reading (Read After Convert)
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
D15
D14
D2
D1
D0
X
1
2
3
14
15
16
t
18
BUSY
SYNC
SCLK
SDOUT
CS
,
RD
CNVST
t
3
t
1
t
17
t
14
t
15
t
19
t
20
t
21
t
16
t
22
t
23
t
24
t
27
t
26
t
25
EXT/
INT
= 0
Figure 18. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)
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相關代理商/技術參數 |
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| AD7677ACPZRL | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LFCSP EP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1MSPS 16BIT PARALLEL/SERL 48LFCSP EP - Tape and Reel |
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