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參數(shù)資料
| 型號： | AD7677 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 1 LSB INL, 1 MSPS Differential ADC |
| 中文描述： | 16位，1 LSB INL和1 MSPS的差分ADC |
| 文件頁數(shù)： | 19/20頁 |
| 文件大小： | 322K |
| 代理商： | AD7677 |
REV. 0
AD7677
–19–
The AD7677 is configured for the internal clock mode (EXT/
INT
low) and acts, therefore, as the master device. The convert com-
mand can be generated by either an external low jitter oscillator
or, as shown, by a FLAG output of the ADSP-21065L, or by a
frame output TFS of one serial port of the ADSP-21065L which
can be used like a timer. The serial port on the ADSP-21065L is
configured for external clock (IRFS = 0), rising edge active
(CKRE = 1), external late framed sync signals (IRFS = 0, LAFS
= 1, RFSR = 1), and active high (LRFS = 0). The serial port of
the ADSP-21065L is configured by writing to its receive control
register (SRCTL)—see ADSP-2106x SHARC User’s Manual.
Because the serial port within the ADSP-21065L will be seeing
a discontinuous clock, an initial word reading has to be done
after the ADSP-21065L has been reset to ensure that the serial
port is properly synchronized to this clock during each following
data read operation.
AD7677
*
ADSP-21065L
*
SHARC
SER/
PAR
RDC/SDIN
RFS
DR
RCLK
FLAG OR TFS
SYNC
SDOUT
SCLK
CNVST
RD
EXT/
INT
CS
INVSYNC
DVDD
*
ADDITIONAL PINS OMITTED FOR CLARITY
INVSCLK
Figure 23. Interfacing to the ADSP-21065L Using the
Serial Master Mode
APPLICATION HINTS
Layout
The AD7677 has very good immunity to noise on the power
supplies as can be seen in Figure 9. However, care should still
be taken with regard to grounding layout.
The printed circuit board that houses the AD7677 should be
designed so the analog and digital sections are separated and
confined to certain areas of the board. This facilitates the use of
ground planes that can be easily separated. Digital and analog
ground planes should be joined in only one place, preferably
underneath the AD7677, or at least as close as possible to the
AD7677. If the AD7677 is in a system where multiple devices
require analog to digital ground connections, the connection
should still be made at one point only, a star ground point,
which should be established as close as possible to the AD7677.
It is recommended to avoid running digital lines under the device
as these will couple noise onto the die. The analog ground
plane should be allowed to run under the AD7677 to avoid
noise coupling. Fast switching signals like
CNVST
or clocks
should be shielded with digital ground to avoid radiating noise
to other sections of the board, and should never run near analog
signal paths. Crossover of digital and analog signals should be
avoided. Traces on different but close layers of the board should
run at right angles to each other. This will reduce the effect of
feedthrough through the board. The power supply lines to the
AD7677 should use as large a trace as possible to provide low
impedance paths and reduce the effect of glitches on the power
supply lines. Good decoupling is also important to lower the
supplies impedance presented to the AD7677 and reduce the
magnitude of the supply spikes. Decoupling ceramic capacitors,
typically 100 nF, should be placed on each power supplies pins
AVDD, DVDD, and OVDD close to, and ideally right up against
these pins and their corresponding ground pins. Additionally,
low ESR 10
μ
F capacitors should be located in the vicinity of
the ADC to further reduce low frequency ripple.
The DVDD supply of the AD7677 can be either a separate
supply or come from the analog supply, AVDD, or from the
digital interface supply, OVDD. When the system digital supply
is noisy, or fast switching digital signals are present, it is recom-
mended if no separate supply available, to connect the DVDD
digital supply to the analog supply AVDD through an RC filter
as shown in Figure 5, and connect the system supply to the inter-
face digital supply OVDD and the remaining digital circuitry.
When DVDD is powered from the system supply, it is useful to
insert a bead to further reduce high-frequency spikes.
The AD7677 has four different ground pins; REFGND, AGND,
DGND, and OGND. REFGND senses the reference voltage
and should be a low impedance return to the reference because
it carries pulsed currents. AGND is the ground to which most
internal ADC analog signals are referenced. This ground must
be connected with the least resistance to the analog ground
plane. DGND must be tied to the analog or digital ground
plane depending on the configuration. OGND is connected to
the digital system ground.
The layout of the decoupling of the reference voltage is impor-
tant. The decoupling capacitor should be close to the ADC and
connected with short and large traces to minimize parasitic
inductances.
Evaluating the AD7677 Performance
A recommended layout for the AD7677 is outlined in the evalu-
ation board for the AD7677. The evaluation board package
includes a fully assembled and tested evaluation board, docu-
mentation, and software for controlling the board from a PC
via the Eval-Control BRD2.
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| AD7677ACPZRL | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LFCSP EP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1MSPS 16BIT PARALLEL/SERL 48LFCSP EP - Tape and Reel |
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