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參數資料
| 型號： | AD7679ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC |
| 中文描述： | 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | LOW PROFILE, MS-026BBC, LQFP-48 |
| 文件頁數： | 15/28頁 |
| 文件大小： | 1186K |
| 代理商： | AD7679ASTRL |
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AD7679
CIRCUIT INFORMATION
Rev. 0 | Page 15 of 28
IN+
REF
REFGND
IN–
MSB
4C
2C
C
C
LSB
SW+
SWITCHES
CONTROL
262,144C 131,072C
MSB
4C
2C
C
C
LSB
SW–
BUSY
OUTPUT
CODE
CNVST
CONTROL
LOGIC
COMP
262,144C 131,072C
03085–0–025
Figure 23. ADC Simplified Schematic
The AD7679 is a very fast, low power, single-supply, precise
18-bit analog-to-digital converter (ADC) using successive
approximation architecture.
CONVERTER OPERATION
The AD7679 is a successive approximation ADC based on a
charge redistribution DAC. Figure 23 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 18 binary weighted capacitors that are
connected to the two comparator inputs.
The AD7679’s linearity and dynamic range are similar or better
than many Σ-Δ ADCs. With the advantages of its successive
architecture, which ease multiplexing and reduce power with
throughput, it can be advantageous in applications that
normally use Σ-Δ ADCs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW–.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on IN+ and IN– inputs. When the
acquisition phase is complete and the CNVST input goes low, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW– are opened first. The two capacitor arrays
are then disconnected from the inputs and connected to the
REFGND input. Therefore, the differential voltage between the
IN+ and IN– inputs captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between REFGND and REF, the comparator input varies
by binary weighted voltage steps (V
REF
/2, V
REF
/4...V
REF
/262144).
The control logic toggles these switches, starting with the MSB
first, to bring the comparator back into a balanced condition.
After completing this process, the control logic generates the
ADC output code and brings the BUSY output low.
The AD7679 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.
The AD7679 can be operated from a single 5 V supply and can
be interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP, or a tiny 48-lead LFCSP that offers space savings
and allows for flexible configurations as either a serial or
parallel interface. The AD7679 is pin-to-pin compatible with
the AD7674, AD7676, and AD7678.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD7679ASTZ | 功能描述:IC ADC 18BIT 570KSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 標準包裝:1 系列:microPOWER™ 位數:8 采樣率（每秒）:1M 數據接口:串行，SPI? 轉換器數目:1 功率耗散（最大）:- 電壓電源:模擬和數字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數目和類型:8 個單端，單極 產品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7679ASTZ | 制造商:Analog Devices 功能描述:IC 18-BIT ADC |
| AD7679ASTZRL | 功能描述:IC ADC 18BIT SAR W/BUFF 48LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:PulSAR® 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
| AD7679CB1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC |
| AD767A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Microprocessor-Compatible 12-Bit D/A Converter |
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