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參數(shù)資料
| 型號(hào)： | CPC700 |
| 廠商： | IBM Microeletronics |
| 英文描述： | Memory Controller and PCI Bridge(存儲(chǔ)器控制器和PCI橋（連接Power PC處理器和PCI總線）) |
| 中文描述： | 內(nèi)存控制器和PCI橋（存儲(chǔ)器控制器和的PCI橋（連接的Power PC處理器和的PCI總線）） |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 58K |
| 代理商： | CPC700 |
CPC700 Memory Controller and PCI Bridge
High-performance companion chip for PowerPC 60x and 7xx processors
Overview
The CPC700
TM
Memory Controller and
PCI Bridge brings high-performance,
real-time control to PowerPC 60x/7xx
driven designs. This single-chip micro-
processor companion is specifically
designed for embedded systems to
provide a general purpose bridge to any
PCI bus. The CPC700 companion chip
also includes a high-speed memory
controller, internal peripherals, and
control for external ROM and external
peripherals.
This CPC700 companion chip can
function as a host bridge, as the basis for
an intelligent add-in PCI controller, or in
stand-alone modes. This versatility and
the following features can help lower
costs, enhance board efficiency and
reduce your time-to-market.
PowerPC 60x/7xx interface (66 MHz)
66 MHz SDRAM interface
External peripheral bus
PCI 2.1 compliant interface
(32-bit, 25 to 66 MHz)
Supports internal or external PCI
bus arbitration
Interrupt controller
Programmable timers
Two full-duplex UARTs (16550)
Two I
2
C interfaces
Byte swapping options ease
communication in little-endian systems
JTAG for board-level testing
General
Extensive programmability
Flexible and programmable
error handling
Processor Interface
The PowerPC
TM
processor bus interface
includes the interface to the system
memory controller, as well as the
Processor Local Bus (PLB) master/slave
interface.
1 level processor address pipelining
Processor bus arbiter
L1 cache coherency support
Two 32-byte write buffers
Provides error tracking/status
lwarx/stwx support (reservation cancel-
ling snoops)
Supports Address Only cycle
Memory Controller
This memory controller provides the
local PowerPC processor with a low-
latency access path supporting external
peripherals and 5 banks of local memory.
SDRAM
Up to 4 banks
11x9 to 13x11 addressing (for 2 and 4
internal bank SDRAMs)
8 MB to 512 MB per bank
CPC700 Block Diagram
UART
UART
Timers
I
C
2
JTAG
Interrupt
Controller
Processor Interface
PCI Interface
Memory Controller
(SDRAM, ROM,
Peripherals)
66 MHz Processor Local Bus (PLB)
3
z
I
C
2
32 or 64-Bi t
13-Bi t
Data/Address
Control
32-Bi t
64-Bi t
Control
Data
Addr.
Control
Data
Addr.
64-Bi t
32-Bi t
32-Bi t
32-Bi t
ECC
8-Bi t
OPB
Bridge
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