
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 1999
(All Rights Reserved)
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
CS5320/21/22
24-Bit Variable Bandwidth A/D Converter Chipset
Features
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CMOS A/D Converter Chipset
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Dynamic Range
-
130 dB @ 25 Hz Bandwidth
-
121 dB @ 411 Hz Bandwidth
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Delta-Sigma Architecture
-
Fourth-Order Modulator
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Variable Oversampling: 64X to 4096X
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Internal Track-and-Hold Amplifier
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CS5321 Signal-to-Distortion: 115 dB
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Clock Jitter Tolerant Architecture
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Input Voltage Range: +4.5 V
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Flexible Filter Chip
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Hardware or Software Selectable Options
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Seven Selectable Filter Corners (-3 dB)
Frequencies: 25, 51, 102, 205, 411, 824 and
1650 Hz
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Low Power Dissipation: <100 mW
Description
The CK5320 and CK5321 Chipsets function as a unique
A/D converter intended for very high resolution measure-
ment of signals below 1500 Hz. The CK5320 Chipset is
a cost effective commercial grade solution for applica-
tions which require a high dynamic range A/D converter.
The chipsets perform sampling, A/D conversion, and
anti-alias filtering.
The CS5320 and CS5321 use Delta-Sigma modulation
to produce highly accurate conversions. The
Σ
modula-
tor oversamples, virtually eliminating the need for
external analog anti-alias filters. The CS5322 linear-
phase FIR digital filter decimates the output to any one
of seven selectable update periods: 16, 8, 4, 2, 1, 0.5
and 0.25 milliseconds. Data is output from the digital fil-
ter in a 24-bit serial format.
ORDERING INFORMATION*
* Refer to Table 5
Chip Sets
Kits
CS5320-KL & CS5322-KL CK5320-KL1
CS5321-BL & CS5322-KL CK5321-KL1
CS5321-BL & CS5322-BL CK5321-BL1
RSEL
SCLK
V
dd1
AINR
AIN+
AIN-
V
ss1
AGND
Analog
Modulator
MDATA
MCLK
MFLG
RESET
R/W
H/S
SID
SOD
ERROR
DRDY
ORCAL
DECA
DECB
DECC
CS
CLKIN
SYNC
VD+
TDATA
PWDN
USEOR
DGND
VD+
DGND
CSEL
Digital
Filter
CS5320/21
CS5322
V
ss2
DGND
V
dd2
LPWR
OFST
MDATA
HBR
MSYNC
VREF+
VREF-
OCT ‘99
DS454PP1