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參數資料
| 型號： | DDU12H-1000C4 |
| 廠商： | DATA DELAY DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 5-TAP, ECL-INTERFACED FIXED DELAY LINE |
| 中文描述： | ACTIVE DELAY LINE, TRUE OUTPUT, PDSO24 |
| 封裝： | SMD-24 |
| 文件頁數： | 4/4頁 |
| 文件大小： | 155K |
| 代理商： | DDU12H-1000C4 |
DDU12H
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
o
C
±
3
o
C
Supply Voltage (Vcc):
-5.0V
±
0.1V
Input Pulse:
Source Impedance:
Rise/Fall Time:
Pulse Width:
Period:
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
OUTPUT:
Load:
C
load
:
Threshold:
(V
OH
+ V
OL
) / 2
(Rising & Falling)
50
to -2V
5pf
±
10%
Standard 10KH ECL
levels
50
Max.
2.0 ns Max. (measured
between 20% and 80%)
PW
IN
= 1.5 x Total Delay
PER
IN
= 10 x Total Delay
T1
OUT
TRIG
IN
REF
TRIG
Test Setup
DEVICE UNDER
TEST (DUT)
OSCILLOSCOPE
PULSE
GENERATOR
IN
T2
T3
T4
T5
T6
T7
T8
T9
T10
Timing Diagram For Testing
T
RISE
T
FALL
PER
IN
PW
IN
T
RISE
T
FALL
20%
20%
80%
50%
50%
50%
V
IH
V
IL
V
OH
V
OL
INPUT
SIGNAL
OUTPUT
SIGNAL
Doc #97036
5/3/2006
DATA DELAY DEVICES, INC.
4
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
相關PDF資料 |
PDF描述 |
|---|---|
| DDU12H-1000M | 5-TAP, ECL-INTERFACED FIXED DELAY LINE |
| DDU12H-1000MC4 | 5-TAP, ECL-INTERFACED FIXED DELAY LINE |
| DDU12H-100C4 | 5-TAP, ECL-INTERFACED FIXED DELAY LINE |
| DDU12H-100MC4 | 5-TAP, ECL-INTERFACED FIXED DELAY LINE |
| DDU12H-10C4 | 5-TAP, ECL-INTERFACED FIXED DELAY LINE |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DDU12H-1000M | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-TAP, ECL-INTERFACED FIXED DELAY LINE |
| DDU12H-1000MC3 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-TAP, ECL-INTERFACED FIXED DELAY LINE (SERIES DDU12H) |
| DDU12H-1000MC4 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-TAP, ECL-INTERFACED FIXED DELAY LINE |
| DDU12H-100C3 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-TAP, ECL-INTERFACED FIXED DELAY LINE (SERIES DDU12H) |
| DDU12H-100C4 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-TAP, ECL-INTERFACED FIXED DELAY LINE |
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