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參數(shù)資料
| 型號： | DDU12H-50MC3 |
| 廠商： | DATA DELAY DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 5-TAP, ECL-INTERFACED FIXED DELAY LINE (SERIES DDU12H) |
| 中文描述： | ACTIVE DELAY LINE, TRUE OUTPUT, DSO24 |
| 封裝： | SMD-24 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大小： | 43K |
| 代理商： | DDU12H-50MC3 |
DDU12H
Doc #97036
12/11/97
DATA DELAY DEVICES, INC.
2
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
APPLICATION NOTES
HIGH FREQUENCY RESPONSE
The DDU12H tolerances are guaranteed for input
pulse widths and periods greater than those
specified in the test conditions. Although the
device will function properly for pulse widths as
small as 10% of the total delay and periods as
small as 20% of the total delay (for a symmetric
input), the delays may deviate from their values
at low frequency. However, for a given input
condition, the deviation will be repeatable from
pulse to pulse. Contact technical support at Data
Delay Devices if your application requires device
testing at a specific input condition.
POWER SUPPLY BYPASSING
The DDU12H relies on a stable power supply to
produce repeatable delays within the stated
tolerances. A 0.1uf capacitor from VEE to GND,
located as close as possible to the VEE pin, is
recommended. A wide VEE trace and a clean
ground plane should be used.
DEVICE SPECIFICATIONS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Storage Temperature
Lead Temperature
SYMBOL
V
EE
V
IN
T
STRG
T
LEAD
MIN
-7.0
MAX
0.3
0.3
150
300
UNITS
V
V
C
C
NOTES
V
EE
- 0.3
-55
10 sec
TABLE 2: DC ELECTRICAL CHARACTERISTICS
(0C to 75C)
PARAMETER
High Level Output Voltage
Low Level Output Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
SYMBOL
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
MIN
-1.020
-1.950
TYP
MAX
-0.735
-1.600
-1.070
UNITS
V
V
V
V
μ
A
μ
A
NOTES
V
IH
= MAX,50
to -2V
V
IL
= MIN, 50
to -2V
-1.480
475
V
IH
= MAX
V
IL
= MIN
0.5
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| DDU12H-750C3 | 5-TAP, ECL-INTERFACED FIXED DELAY LINE (SERIES DDU12H) |
| DDU12H-750M | 5-TAP, ECL-INTERFACED FIXED DELAY LINE (SERIES DDU12H) |
| DDU12H-750MC3 | 5-TAP, ECL-INTERFACED FIXED DELAY LINE (SERIES DDU12H) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DDU12H-50MC4 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-TAP, ECL-INTERFACED FIXED DELAY LINE |
| DDU12H-75 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-TAP, ECL-INTERFACED FIXED DELAY LINE |
| DDU12H750 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| DDU12H-750 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-TAP, ECL-INTERFACED FIXED DELAY LINE |
| DDU12H-750C3 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-TAP, ECL-INTERFACED FIXED DELAY LINE (SERIES DDU12H) |
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