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參數(shù)資料
| 型號(hào)： | EDI2AG27265V12D1 |
| 英文描述： | 2x64Kx72, 3.3V,12ns, Sync/Sync Burst SRAM Module(2x64Kx72, 3.3V，12ns,同步/同步脈沖靜態(tài)RAM模塊) |
| 中文描述： | 2x64Kx72，3.3伏，12ns，同步/同步突發(fā)靜態(tài)存儲(chǔ)器模塊（2x64Kx72，3.3伏，12ns，同步/同步脈沖靜態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 2802K |
| 代理商： | EDI2AG27265V12D1 |
1
EDI2AG27265V
White Electronic Designs Corporation Westborough, MA 01581
(508) 366-5151 www.whiteedc.com
July1999 Rev
ECO
1 Megabyte Sync/Sync Burst, Small Outline DIMM
FEATURES
PIN NAMES
The EDI2AG27265VxxD1 is a Synchronous/Synchronous Burst
SRAM, 72 position 30 DIMM(144 contacts) Module, organized as
2x64Kx72. The Module contains four (4) Synchronous Burst Ram
Devices, packaged in the industry standard JEDEC 14mmx20mm
TQFPplacedonaMultilayerFR4Substrate. Themodulearchitecture
is defined as a Sync/Sync Burst, Flow-Through, with support for
either linear or sequential burst. This module provides High
Performance,2-1-1-1accesseswhenusedinBurstMode,andused
as a Synchronous Only Mode, provides a high performance cost
advantage over BiCMOS aysnchronous device architectures.
Synchronous Only operations are performed via strapping ADSC\
Low, and ADSP\ / ADV\ High, which provides for Ultra Fast
AccessesinReadModewhileprovidingforinternallyself-timedEarly
Writes.
Synchronous/Synchronous Burst operations are in relation to an
externally supplied clock, Registered Address, Registered Global
Write,RegisteredEnablesaswellasanAsynchronousOutputenable.
This Module has been defined with full flexibility, which allows
individual control of each of the eight bytes, as well as Quad Words
in both Read and Write Operations.
2x64kx72 Synchronous, Synchronous Burst
Flow-Through Architecture
Sequential Burst MODE
Clock Controlled Registered Bank Enables (E1\,
E2)
Clock Controlled Byte Write Mode Enable (BWE\)
Clock Controlled Byte Write Enables (BW1\ - BW8\)
Clock Controlled Registered Address
Clock Controlled Registered Global Write (GW\)
Aysnchronous Output Enable (G\)
Internally self-timed Write
Gold Lead Finish
3.3V +10% Operation
Access Speed(s): TKHQV=8.5, 9, 10, 12ns
Common Data I/O
High Capacitance (30pf) drive, at rated Access
Speed
Single total array Clock
Multiple Vcc and Gnd
DQ0-DQ63
Input/Output Bus
DQP0-DQP7
Parity Bits
A0-A15
Address Bus
E1\, E2
SynchronousBankEnables
BWE\
Byte Write Mode Enable
BW1\-BW8\
Byte Write Enables
Clk
Array Clock
GW\
Synchronous Global write Enable
G\
Asynchronous Output Enable
Vcc
3.3V Power Supply
Vss
Gnd
相關(guān)PDF資料 |
PDF描述 |
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| EDI2AG27265V85D1 | 2x64Kx72, 3.3V,8.5ns, Sync/Sync Burst SRAM Module(2x64Kx72, 3.3V，8.5ns,同步/同步脈沖靜態(tài)RAM模塊) |
| EDI2AG27265V9D1 | 2x64Kx72, 3.3V,9ns, Sync/Sync Burst SRAM Module(2x64Kx72, 3.3V，9ns,同步/同步脈沖靜態(tài)RAM模塊) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDI2CG272128V | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
| EDI2CG272128V12D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
| EDI2CG272128V15D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
| EDI2CG272128V85D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
| EDI2CG272128V9D1 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM |
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