- 您現在的位置：買賣IC網 > PDF目錄97875 > EDI2CG472256V12D2 4x256Kx72, 3.3V Synchronous/Synchronous Burst Flow-Through(4x256Kx72, 3.3V，12ns,同步/同步脈沖靜態RAM模塊(流通結構）) PDF資料下載
參數資料
| 型號： | EDI2CG472256V12D2 |
| 英文描述： | 4x256Kx72, 3.3V Synchronous/Synchronous Burst Flow-Through(4x256Kx72, 3.3V，12ns,同步/同步脈沖靜態RAM模塊(流通結構）) |
| 中文描述： | 4x256Kx72，3.3同步/同步突發流量通過（4x256Kx72，3.3伏，12ns，同步/同步脈沖靜態內存模塊（流通結構）） |
| 文件頁數： | 1/12頁 |
| 文件大?。?/td> | 366K |
| 代理商： | EDI2CG472256V12D2 |
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI2CG472256V
August 1998 Rev. 1
ECO #10656
4x256Kx72, 3.3V Synchronous/Synchronous Burst Flow-Through
FEATURES
s 4x256Kx72 Synchronous, Synchronous Burst
s Flow-Through Architecture
s Linear and Sequential Burst Support via MODE pin
s Clock Controlled Registered Module Enable (EM\)
s Clock Controlled Registered Bank Enables (E1\, E2\, E3\, E4\)
s Clock Controlled Byte Write Mode Enable (BWE\)
s Clock Controlled Byte Write Enables (BW1\ - BW8\)
s Clock Controlled Registered Address
s Clock Controlled Registered Global Write (GW\)
s Aysnchronous Output Enable (G\)
s Internally self-timed Write
s Individual Bank Sleep Mode enables (ZZ1, ZZ2, ZZ3, ZZ4)
s Gold Lead Finish
s 3.3V
±10%, - 5% Operation
s Access Speed(s): tKHQV = 9, 10, 12, 15ns
s Common Data I/O
s High Capacitance (30pF) drive, at rated Access Speed
s Single total array Clock
s Multiple Vcc and Gnd
The EDI2CG472256VxxD2 is a Synchronous/Synchronous Burst
SRAM, 84 position Dual Key; Double High DIMM (168 contacts)
Module, organized as 4x256Kx72. The Module contains sixteen
(16) Synchronous Burst Ram Devices, packaged in the industry
standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4
Substrate. The module architecture is defined as a Sync/Sync
Burst, Flow-Through, with support for either linear or sequential
burst. This module provides High Performance, 2-1-1-1 accesses
when used in Burst Mode, and used as a Synchronous Only Mode,
provides a high performance cost advantage over BiCMOS
aysnchronous device architectures.
Synchronous Only operations are performed via strapping ADSC\
Low, and ADSP\ / ADV\ High, which provides for Ultra Fast
Accesses in Read Mode while providing for internally self-timed
Early Writes.
Synchronous/Synchronous Burst operations are in relation to an
externally supplied clock, Registered Address, Registered Global
Write, Registered Enables as well as an Asynchronous Output
enable. This Module has been defined with full flexibility, which
allows individual control of each of the eight bytes, as well as
Quad Words in both Read and Write Operations.
相關PDF資料 |
PDF描述 |
|---|---|
| EDI2CG472256V15D2 | 4x256Kx72, 3.3V Synchronous/Synchronous Burst Flow-Through(4x256Kx72, 3.3V，15ns,同步/同步脈沖靜態RAM模塊(流通結構）) |
| EDI2CG472256V9D2 | 4x256Kx72, 3.3V Synchronous/Synchronous Burst Flow-Through(4x256Kx72, 3.3V，9ns,同步/同步脈沖靜態RAM模塊(流通結構）) |
| EDI411024C80FC | x1 Fast Page Mode DRAM |
| EDI411024C80FI | x1 Fast Page Mode DRAM |
| EDI411024C80FM | x1 Fast Page Mode DRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| EDI2CG472256V15D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8 Megabyte Sync/Sync Burst, Dual Key DIMM |
| EDI2CG472256V9D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8 Megabyte Sync/Sync Burst, Dual Key DIMM |
| EDI2CG472256V-D2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SSRAM Modules |
| EDI2DL32256V | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256Kx32 Synchronous Pipline Burst SRAM 3.3V |
| EDI2DL32256V35BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256Kx32 Synchronous Pipline Burst SRAM 3.3V |
發布緊急采購，3分鐘左右您將得到回復。