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參數資料
| 型號： | ICS8432DYI-101LF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數： | 1/20頁 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER 700MHZ 32-LQFP |
| 標準包裝： | 250 |
| 系列： | HiPerClockS™ |
| 類型： | 頻率合成器 |
| PLL： | 帶旁路 |
| 輸入： | HCSL，LVDS，LVHSTL，LVPECL，SSTL |
| 輸出： | LVPECL |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 700MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應商設備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤 |
| 其它名稱： | 8432DYI-101LF |
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
ICS8432I-101
IDT / ICS 700MHZ, 3.3V LVPECL FREQUENCY SYNTHESIZER
1
ICS8432DYI-101 REV. C APRIL 10, 2007
GENERAL DESCRIPTION
The ICS8432I-101 is a general purpose, dual out-
put Differential-to-3.3V LVPECL high frequency
synthesizer and a member of the HiPerClockS
family of High Performance Clock Solutions from
IDT. The ICS8432I-101 has a selectable
TEST_CLK or CLK, nCLK inputs. The TEST_CLK input accepts
LVCMOS or LVTTL input levels and translates them to 3.3V
LVPECL levels. The CLK, nCLK pair can accept most standard
differential input levels. The VCO operates at a frequency
range of 250MHz to 700MHz. The VCO frequency is pro-
grammed in steps equal to the value of the input differential
or single ended reference frequency. The VCO and output
frequency can be programmed using the serial or parallel
interfaces to the configuration logic. The low phase noise
characteristics of the ICS8432I-101 makes it an ideal clock
source for Gigabit Ethernet and SONET applications.
BLOCK DIAGRAM
PIN ASSIGNMENT
FEATURES
Dual differential 3.3V LVPECL outputs
Selectable CLK, nCLK or LVCMOS/LVTTL TEST_CLK
TEST_CLK can accept the following input levels:
LVCMOS or LVTTL
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
CLK, nCLK or TEST_CLK maximum input frequency: 40MHz
Output frequency range: 25MHz to 700MHz
VCO range: 250MHz to 700MHz
Accepts any single-ended input signal on CLK input with
resistor bias on nCLK input
Parallel interface for programming counter and output
dividers
RMS period jitter: 5ps (maximum)
Cycle-to-cycle jitter: 25ps (maximum)
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
CLK
TEST_CLK
CLK_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
M5
M6
M7
M8
N0
N1
nc
VEE
V
EE
nFOUT0
FOUT0
V
CCO
nFOUT1
FOUT1
V
CC
TEST
nCLK
nP_LO
A
D
VCO_SEL
M0
M1
M2
M3
M4
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8432I-101
VCO_SEL
CLK_SEL
TEST_CLK
CLK
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
VCO
PLL
FOUT0
nFOUT0
FOUT1
nFOUT1
TEST
CONFIGURATION
INTERFACE
LOGIC
÷ M
0
1
0
1
PHASE DETECTOR
÷1
÷2
÷4
÷8
MR
nCLK
HiPerClockS
ICS
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ICS8432DYI-101LFT | 功能描述:IC SYNTHESIZER 700MHZ 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:HiPerClockS™ 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數:- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS8432DYI-101T | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8432I-101 | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8432I-51 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS84330 | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
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