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參數資料
| 型號： | ISL25700FRUZ-TK |
| 廠商： | Intersil |
| 文件頁數： | 7/18頁 |
| 文件大小： | 441K |
| 描述： | IC TEMP SWITCH MFET DRVR 10TQFN |
| 標準包裝： | 1,000 |
| 功能： | 溫度監控系統（傳感器），溫度開關 |
| 傳感器類型： | 外部 |
| 感應溫度： | 40°C ~ 110°C 跳變點 |
| 精確度： | ±3°C |
| 拓撲： | 比較器，電壓基準 |
| 輸出類型： | 電壓 |
| 輸出警報： | 無 |
| 輸出風扇： | 無 |
| 電源電壓： | 3 V ~ 15 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-UFQFN |
| 供應商設備封裝： | 10-UTQFN（2.1x1.6） |
| 包裝： | 帶卷 (TR) |
ISL25700
7
FN6885.0
September 3, 2010
t
AA
(Note 11)
SCL Falling Edge to SDA
Output Data Valid
SCL falling edge crossing 30% of V
I2C
,
until SDA exits the 30% to 70% of
V
I2C
window
900
ns
t
BUF
(Note 11)
Time the Bus Must be Free
Before the Start of a New
Transmission
SDA crossing 70% of V
I2C
during a
STOP condition, to SDA crossing 70%
of V
I2C
during the following START
condition
1300
ns
t
LOW
Clock LOW Time
Measured at the 30% of V
I2C
crossing
1300
ns
t
HIGH
Clock HIGH Time
Measured at the 70% of V
I2C
crossing
600
ns
t
SU:STA
START Condition Setup Time SCL rising edge to SDA falling edge.
Both crossing 70% of V
I2C
.
600
ns
t
HD:STA
START Condition Hold Time
From SDA falling edge crossing 30%
of V
I2C
to SCL falling edge crossing
70% of V
I2C
600
ns
t
SU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of
V
I2C
window, to SCL rising edge
crossing 30% of V
I2C
100
ns
t
HD:DAT
Input Data Hold Time
From SCL falling edge crossing 70% of
V
I2C
to SDA entering the 30% to 70%
of V
I2C
window
0
ns
t
SU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of
V
I2C
, to SDA rising edge crossing 30%
of V
I2C
600
ns
t
DH
Output Data Hold Time
From SCL falling edge crossing 30% of
V
I2C
, until SDA enters the 30% to
70% of V
I2C
window
0
ns
t
R
SDA and SCL Rise Time
From 30% to 70% of V
I2C
20 +
0.1 * Cb
250
ns
t
F
SDA and SCL Fall Time
From 70% to 30% of V
I2C
20 +
0.1 * Cb
250
ns
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
Rpu
(Note 11)
SDA and SCL Bus Pull-Up
Resistor Off-Chip
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about 2~2.5k?
For Cb = 40pF, max is about 15~20k?/DIV>
1
k?/DIV>
t
WC
(Notes
11, 12)
Non-Volatile Write Cycle Time
15
20
ms
NOTES:
6. Typical values are for T
A
= +25癈 and 12V supply voltage.
7. LSB: [VDAC
255
VDAC
0
]/255. VDAC
255
and VDAC
0
are the DAC output voltage when DAC register set to FF hex and 00 hex
respectively.
8. DNL = [VDAC
i
VDAC
i-1
]/LSB-1, for i = 1 to 255. i is the DAC register setting.
9. INL = [VDAC
i
(i " LSB + VDAC
0
)]/LSB for i = 1 to 255.
10.
for i = 1 to 255 decimal, T = -40癈 to +125癈, referenced to 40癈.
11. Limits established by characterization and are not production tested.
12. t
WC
is the time from a valid STOP condition at the end of a Write sequence of a I
2
C serial interface Write operation, to the
end of the self-timed internal non-volatile write cycle. The Busy Polling method can be used to determine the end of the
non-volatile write cycle.
13. Parameters with MIN and/or MAX limits are 100% tested at +25癈, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
14. B
25/85
is a thermistor material specific constant; represents the slope of the Resistance vs. Temperature curve.
Operating Specifications Over the recommended operating conditions unless otherwise specified. Boldface limits
apply over the operating temperature range, -40癈 to +125癈. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 13)
TYP
(Note 6)
MAX
(Note 13) UNITS
TC
V
VDAC
i
T
( ) VDAC
i
40癈
(
)
VDAC
i
40癈
(
)
------------------------------------------------------------------------ -
10
6
T 40
(
)癈
--------------------------- -
?/DIV>
=
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