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| 型號(hào)： | ISL6173DRZA-T |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 13/20頁(yè) |
| 文件大小： | 453K |
| 描述： | IC CTRLR HOT SWAP DUAL LV 28-QFN |
| 標(biāo)準(zhǔn)包裝： | 6,000 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開(kāi)關(guān)： | 無(wú) |
| 電源電壓： | 2.25 V ~ 3.63 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-QFN 裸露焊盤（5x5） |
| 包裝： | 帶卷 (TR) |
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13
FN9186.3
January 3, 2006
Applications Information
Selection of External Components
The typical application circuit of Figure 2 has been used for
this section, which provides guidelines to select the external
component values.
MOSFET (Q1)
This component should be selected on the basis of its
r
DS(ON)
specification at the expected Vgs (gate to source
voltage) and the effective input gate capacitance (Ciss). One
needs to ensure that the combined voltage drop across the
Rsense and r
DS(ON)
at the desired maximum current
(including transients) will still keep the output voltage above
the minimum required level. Power dissipation in the device
under short circuit condition should also be an important
consideration especially in auto-retry mode (RTR
/LTCH pin
pulled low). Using ISL6173 in latched off mode results in
lower power dissipation in the MOSFET.
Ciss of the MOSFET influences the overcurrent response
time. It is recommended that a MOSFET with Ciss of less
than 10nF be chosen. Ciss will also have an impact on the
SS cap value selection as seen later.
Current Sense Resistor (R
SNS
)
The voltage drop across this resistor, which represents the
load current (Io), is compared against the set threshold of
the current regulation amplifier. The value of this resistor is
determined by how much combined voltage drop is tolerable
between the source and the load. It is recommended that at
least 20mV drop be allowed across this resistor at max load
current. This resistor is expected to carry maximum full load
current indefinitely. Hence, the power rating of this resistor
must be greater than I
O(MAX)
2
*R
SNS
.
This resistor is typically a low value resistor and hence the
voltage signal appearing across it is also small. In order to
maintain high current sense accuracy, current sense trace
routing is critical. It is recommended that either a four wire
resistor or the following routing method be used:
Current Set Resistor (R
SET)
This resistor directly sets the threshold for the current
regulation amplifier and indirectly sets the same for the OC
and WOC comparators in conjunction with R
SNS
. Once
R
SNS
has been selected, use Equation 1 (on page 9) to
calculate R
SET
. Use 20礎(chǔ) for I
SET
in a typical application.
Reference Current Set Resistor (R
REF
)
This resistor sets up the current in the internal current
source, I
REF
/4, shown in Figure 2 for the comparators. The
voltage at the OCREF pin is the same as the internal
bandgap reference. The current (I
REF
) flowing through this
resistor is simply:
I
REF
= 1.178/R
REF
This current, I
REF
, should be set at 80礎(chǔ) to force 20礎(chǔ) in the
internal current source as shown in Figure 2, because of the
4:1 current mirror. This equates to the resistor value of
14.7K.
Selection of Rs1 and Rs2
These resistors set the UV detect point. The UV comparator
detects the undervoltage condition when it sees the voltage
at UV pin drop below 0.633V. The resistor divider values
should be selected accordingly.
Charge Pump Capacitor Selection (C
P
and C
V
)
C
P
is the flying cap and C
V
is the smoothing cap of the
charge pump, which operates at 450kHz set internally. The
output resistance of the charge pump, which affects the
regulation, is dependent on the C
P
value and its ESR,
charge-pump switch resistance, and the frequency and ESR
of the smoothing cap, C
V
.
It is recommended that C
P
be kept within 0.022礔
(minimum) to 0.1礔 (maximum) range. Only ceramic
capacitors are recommended. Use 0.1礔 cap if CPVDD
output is expected to power an external circuit, in which case
the current draw from CPVDD must be kept below 10mA.
C
V
should at least be 0.47礔 (ceramic only). Higher values
may be used if low ripple performance is desired.
Time-out Capacitor Selection (C
T
)
This capacitor controls the current regulation time-out
period. As shown in Figure 2, when the voltage across this
capacitor exceeds 1.178V, the time-out comparator detects it
and pulls down the gate voltage thus shutting down the
channel. An internal 10礎(chǔ) current source charges this
capacitor. Hence, the value of this capacitor is determined by
the following equation:
C
T
= (10礎(chǔ) * T
OUT
)/1.178
Where,
T
OUT
= Desired time-out period.
LOAD CURRENT CARRYING
TRACES
R
SNS
CURRENT
SENSE
TRACES
FIGURE 17. RECOMMENDED CURRENT SENSE RESISTOR
PCB LAYOUT
ISL6173
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