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參數資料
| 型號： | ISL6432CB-T |
| 廠商： | Intersil |
| 文件頁數： | 10/12頁 |
| 文件大?。?/td> | 274K |
| 描述： | IC REG QD BCK/LINEAR 16-SOIC |
| 標準包裝： | 2,500 |
| 拓撲： | 降壓（降壓）同步（1），線性（LDO）（3） |
| 功能： | 任何功能 |
| 輸出數： | 4 |
| 頻率 - 開關： | 300kHz |
| 電壓/電流 - 輸出 1： | 控制器 |
| 電壓/電流 - 輸出 2： | 控制器 |
| 電壓/電流 - 輸出 3： | 控制器 |
| 帶 LED 驅動器： | 無 |
| 帶監控器： | 無 |
| 帶序列發生器： | 是 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | * |
| 包裝： | 帶卷 (TR) |
10
where: I
TRAN
is the transient load current step, t
RISE
is the
response time to the application of load, and t
FALL
is the
response time to the removal of load. Be sure to check both
of these equations at the minimum and maximum output
levels for the worst case response time.
Input Capacitor Selection
The important parameters for the bulk input capacitors are
the voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maximum input voltage and largest
RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 of the summation of the DC load current.
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitance
for the high frequency decoupling and bulk capacitors to
supply the RMS current. Small ceramic capacitors can be
placed very close to the upper MOSFET to suppress the
voltage induced in the parasitic circuit impedances.
For a through-hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These capacitors
must be capable of handling the surge-current at power-up.
Transistors Selection/Considerations
The ISL6432 requires 5 external transistors. Two N-channel
MOSFETs are used in the synchronous-rectified buck topology
of PWM converter. The clock, AGP and MCH/ICH linear
controllers each drive an NPN bipolar transistor as a pass
element. All these transistors should be selected based upon
r
DS(ON)
, current gain, saturation voltages, gate/base supply
requirements, and thermal management considerations.
PWM MOSFET Selection and Considerations
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes two
loss components; conduction loss and switching loss. These
losses are distributed between the upper and lower
MOSFETs according to duty factor (see the equations
below). The conduction losses are the main component of
power dissipation for the lower MOSFETs. Only the upper
MOSFET has significant switching losses, since the lower
device turns on and off into near zero voltage.
The equations below assume linear voltage-current
transitions and do not model power loss due to the reverse-
recovery of the lower MOSFETs body diode. The gate-
charge losses are dissipated by the ISL6432 and don't heat
the MOSFETs. However, large gate-charge increases the
switching time, t
SW
which increases the upper MOSFET
switching losses. Ensure that both MOSFETs are within their
maximum junction temperature at high ambient temperature
by calculating the temperature rise according to package
thermal-resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
Given the reduced available gate bias voltage (5V) logic-
level or sub-logic-level transistors have to be used for both N-
MOSFETs. Caution should be exercised with devices
exhibiting very low V
GS(ON)
characteristics, as the low gate
threshold could be conducive to some shoot-through (due to
the Miller effect), in spite of the counteracting circuitry
present aboard the ISL6432.
Rectifier CR1 is a clamp that catches the negative inductor
swing during the dead time between the turn off of the lower
MOSFET and the turn on of the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, providing the body diode
is fast enough to avoid excessive negative voltage swings at
the PHASE pin. The diode's rated reverse breakdown
voltage must be greater than the maximum input voltage.
Linear Controllers Transistor Selection
The main criteria for selection of transistors for the linear
regulators is package selection for efficient removal of heat.
The power dissipated in a linear regulator is:
Select a package and heatsink that maintains the junction
temperature below the rating with a the maximum expected
ambient temperature.
As bipolar NPN transistors have to be used with the linear
controllers, insure the current gain at the given operating
V
CE
is sufficiently large to provide the desired maximum
output load current when the base is fed with the minimum
driver output current.
P
UPPER
I
O
2
r
DS ON
( )
?/DIV>
V
OUT
?/DIV>
V
IN
----------------------------------------------------------- -
I
O
V
IN
?/DIV>
t
SW
?/DIV>
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F
S
?/DIV>
2
----------------------------------------------------
+
=
P
LOWER
I
O
2
r
DS ON
( )
?/DIV>
V
IN
V
OUT
(
)
?/DIV>
V
IN
-------------------------------------------------------------------------------- -
=
FIGURE 7. MOSFET GATE BIAS
+5V
PGND
ISL6432
GND
LGATE
UGATE
PHASE
BOOT
+5V OR LESS
NOTE:
NOTE:
V
GS
H
H
H
H V
CC
Q1
Q2
+
-
V
GS
H
H
H
H V
CC
-0.5V
CR1
VCC
C
BOOT
VCC
+
P
LINEAR
I
O
V
IN
V
OUT
(
)
?/DIV>
=
ISL6432
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