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參數資料
| 型號： | M1010-01I155.5200 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 154K |
| 代理商： | M1010-01I155.5200 |
M1010-01 Datasheet Rev 0.5
Revised 30Mar2005
Integ r ated Circuit Systems , Inc. ● Comm unications Modules ● www.icst.com ● tel (508) 852-5400
M1010-01
VCSO BASED CLOCK JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
Prelimina r y Inf o r m ation
GENERAL DESCRIPTION
The M1010-01 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for OC-12 and OC-48 optical
network systems supporting 622 -
2,488 MHz rates. It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1010-01 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
FEATURES
◆ Ideal for OC-12/48 data clock
◆ Integrated SAW delay line
◆ Output frequencies from 150 to 175 MHz
(Specify VCSO output frequency at time of order)
◆ Low phase jitter of 0.5 ps rms, typical (12kHz to 20MHz)
◆ LVPECL clock output
◆ Pin-selectable feedback and reference divider ratios,
no programming required
◆ Scalable dividers provide further adjustment of loop
bandwidth as well as jitter tolerance
◆ Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
PIN ASSIGNMENT (9 x 9 mm SMT)
Figure 1: Pin Assignment
SIMPLIFIED BLOCK DIAGRAM
Figure 2: Simplified Block Diagram
Example I/O Clock Frequency Combinations
Using M1010-01-155.5200
Frequency
Input (Mfin)
Ratio
Input Reference
Clock
(MHz)
Output
Clock MHz
8
19.44
155.52
2
77.76
1
155.52
Table 1: Example I/O Clock Frequency Combinations
M 1010
( T op View )
18
17
16
15
14
13
12
11
10
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
F
IN
_
SEL
1
GN
D
NC
DI
F
_RE
F
0
n
D
IF
_RE
F
0
RE
F
_
S
E
L
DI
F
_RE
F
1
n
D
IF
_RE
F
1
VC
C
VCC
NC
nFOUT
FOUT
GND
NC
VCC
GND
FIN_SEL0
SEL0
SEL1
SEL2
NC
VCC
DNC
nOP
_
IN
O
P
_O
UT
VC
nV
C
nOP
_
OU
T
OP
_
IN
GN
D
GN
D
GN
D
19
20
21
22
23
24
25
26
27
R Div
VCSO
Mfin Div
M Div
Divider LUT
Mfin Divider
LUT
FIN_SEL1:0
REF_SEL
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
0
1
M1010
FOUT
nFOUT
SEL2:0
3
2
Loop
Filter
M1010-01 VCSO Based Clock Jitter Attenuator
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