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參數(shù)資料
| 型號(hào)： | M2006-12-644.5313 |
| 廠(chǎng)商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 374K |
| 代理商： | M2006-12-644.5313 |
M2006-12 Datasheet Rev 1.0
Revised 13Jul2004
Integr a t ed Cir cui t S ystems , Inc . ● N e tw or kin g & C o mm un icat ion s ● www. icst.com ● te l (5 08 ) 85 2-5 4 0 0
M2006-12
VCSO BASED FEC CLOCK PLL
Product Data Sheet
GENERAL DESCRIPTION
The M2006-12 is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock frequency
translation and jitter attenuation.
Clock multiplication ratios (including
forward and inverse FEC) are
pin-selected from pre-programming
look-up tables. Includes Hitless
Switching and Phase Build-out to
enable SONET (GR-253) / SDH (G.813) MTIE and
TDEV compliance during reference clock reselection.
Hitless Switching (HS) engages when a 4ns or greater
clock phase change is detected.
This phase-change triggered implementation of HS is
not recommended when using an unstable reference
(more than 1ns jitter pk-to-pk) or when the resulting
phase detector frequency is less than 5MHz.
FEATURES
◆ Similar to the M2006-02 - and pin-compatible - but adds
Hitless Switching and Phase Build-out functions
◆ Includes APC pin for Phase Build-out function (for
absorption of the input phase change)
◆ Pin-selectable PLL divider ratios support forward and
inverse FEC ratio translation
◆ Supports input reference and VCSO frequencies up to
700MHz (Specify VCSO frequency at time of order)
◆ Low phase jitter < 0.5 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
◆ Commercial and Industrial temperature grades
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
PIN ASSIGNMENT (9 x 9 mm SMT)
Figure 1: Pin Assignment
SIMPLIFIED BLOCK DIAGRAM
Figure 2: Simplified Block Diagram
Example I/O Clock Frequency Combinations
Using M2006-12-622.0800 and Inverse FEC Ratios
FEC PLL Ratio
Mfec / Rfec
Base Input Rate 1
(MHz)
Note 1: Input reference clock can be the base frequency shown
Output Clock
(either output)
MHz
1/1
622.0800
622.08
or
155.52
238/255
666.5143
237/255
669.3266
236/255
672.1627
P0_SEL
P1_SEL
M2006-12
Loop
Filter
M2006-12 VCSO Based FEC Clock PLL
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M2006-12A | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING |
| M2006-12A-622.0800 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING |
| M2006-12A-625.0000 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING |
| M2006-12A-669.3266 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING |
| M2006-12A-669.6429 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING |
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