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| 型號： | MB84VP24491HK-70PBS |
| 廠商： | Fujitsu Limited |
| 英文描述： | RES NET BUSSED 150 OHM 6-SIP |
| 中文描述： | 128M的（x16）的快閃記憶體32M的（x16）的移動FCRAMTM |
| 文件頁數： | 45/70頁 |
| 文件大?。?/td> | 1272K |
| 代理商： | MB84VP24491HK-70PBS |
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MB84VP24491HK
-70
44
I
32 M FCRAM CHARACTERISTICS for MCP
1.
Power Down (32M Page Mode FCRAM)
Power Down (32M Page mode FCRAM)
The Power Down is to enter low power idle state when CE2r stays Low.
The 32M page mode FCRAM has four power down mode, Sleep, 4M Partial, 8M Partial, and 16M Partial.
These can be programmed by series of read/write operation. Each mode has follwoing features.
The default state is Sleep and it is the lowest power consumption but all data will be lost once CE2r is brought
to Low for Power Down. It is not required to program to Sleep mode after power-up.
Power Down Program Sequence (32M Page mode FCRAM)
The program requires total 6 read/write operation with unique address and data. Between each read/write
operation requires that device be in standby mode. Following table shows the detail sequence.
The first cycle is to read from most significient address (MSB).
The second and third cycle are to write back the data (RDa) read by first cycle. If the third cycle is written into
the different address, the program is cancelled and the data written by the second or third cycle is valid as a
normal write operation.
The forth and fifth cycle is to write the data key for program. The data of forth cycle must be all 0’s and data of
fifth cycle is a data key for mode selection. If the forth cycle is written into different address, the program is also
cancelled.
The last cycle is to read from specific address key for mode selection. The both data key written by fifth cycle
and address key must be the same mode for proper programming.
Once this program sequence is performed from a Partial mode to other Partial mode, the write data may be lost.
So, it should perform this program prior to regular read/write operation if Partial mode is used.
Mode
Data Retention
Retention Address
Sleep (default)
No
N/A
4M Partial
4M bit
00000h to 3FFFFh
8M Partial
8M bit
00000h to 7FFFFh
16M Partial
16M bit
00000h to FFFFFh
Cycle #
Operation
Address
Data
1st
Read
1FFFFFh (MSB)
Read Data (RDa)
2nd
Write
1FFFFFh
RDa
3rd
Write
1FFFFFh
RDa
4th
Write
1FFFFFh
0000h
5th
Write
1FFFFFh
Data Key
6th
Read
Address Key
Read Data (RDb)
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