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| 型號(hào)： | MBM30LV0128-PFTR |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | 128 M (16 M X 8) BIT NAND-type |
| 中文描述： | 16M X 8 FLASH 2.7V PROM, PDSO48 |
| 封裝： | PLASTIC, REVERSE, TSOP-48 |
| 文件頁(yè)數(shù)： | 10/43頁(yè) |
| 文件大小： | 397K |
| 代理商： | MBM30LV0128-PFTR |
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MBM30LV0064
10
Read (3): 50h
The Read (3) mode has identical timing to that of Read (1) and (2). However, while Read (1) and (2) are used
to access the array, Read (3) is used to access the 16 byte spare area. When the 50h command is executed,
the pointer will be set to an address space between columns 512 and 527. The values of Y will complete the
address decoding. During this operation, only address bits A
3
to A
0
are used to determine the starting column
address; A
7
to A
4
are ignored. A
22
to A
9
are used to determine the starting row address.
Sequential Read
Each RE pulse used to output data from the data register will cause the column address pointer to increment
by one. When the final column has been reached, the next page will be automatically loaded into the data register.
The R/B signal may be used to monitor the completion of the data transfer.
CLE
CE
WE
ALE
RE
I/O0
to I/O7
Y
X
X
R/B
50h
Data Output
Starting Address
Command
0
255
511 527
(Column Address)
Page (Row)
Address
X
Y
Figure 3 Read Mode (3) Operation
0
I/O0 to I/O7
R/B
Address Input
Data
Data
Data
00h/01h/50h
0
255
511 527
50h, SE=L
0
255
511 527
00h, SE=H
0
255
511 527
01h, SE=L
255
511 527
00h, SE=L
Figure 4 Sequential Read
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