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參數資料
| 型號： | MC68040 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Errata and Added Information to MC68360 Quad Integrated Communication Controller User Manual Rev 1 |
| 中文描述： | 勘誤表和新增的資料MC68360四綜合通信控制器用戶手冊修訂1 |
| 文件頁數： | 14/28頁 |
| 文件大小： | 159K |
| 代理商： | MC68040 |
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14
MC68360 USER’S MANUAL ERRATA
MOTOROLA
27. Typo on Table 7-11.
On page 7-248, the last three entries of Table 7-11 were mistyped.The correct entries are:
28. Missing Bit in Ethernet Receive Buffer Descriptor.
On page 7-260, the figure of the receive buffer descriptor is not correct. The correct figure is
:
29. Replace the DEF Explanation.
On Page 7-263, section 7.10.23.19, the DEF—Defer Indication explanation should be
replaced with the following paragraph:
This frame was deferred before being successfully sent. Deferral means that the the
transmitter had to wait for carrier sense before sending because the line was busy. This is
not an indication of a collision; collisions are indicated in the Retry Count (RC).
30. Additional Information on Using TSA for Synchronization.
On Page 7-296, section 7.11.10.7, the second paragraph from the bottom is not sufficient
and should be replaced with the following paragraph:
Once the TEN bit is set in SMCMR, the SMC waits for the transmit FIFO to be loaded before
attempting to achieve synchronization. Once the transmit FIFO is loaded, synchronization
and transmission begin according to the following conditions.
If a buffer is made ready when the SMC is enabled, then the first byte will be placed in time
slot 1 if CLSN is set to 8 and slot 2 if CLSN is set to 16.
If a buffer has its SMC is enabled, then the first byte in the next buffer can appear in any time
slot associated with this channel.
If a buffer is ended with the L-bit set, then the next buffer can appear in any time slot
associated with this channel.
SCC Base + 9E
SCC Base + A0
SCC Base + A2
TADDR_H
TADDR_M
TADDR_L
Word
Word
Word
Temp Address (LSB)
Temp Address
Temp Address (MSB)
2
OFFSET + 0
OFFSET + 2
E
—
W
I
L
F
—
M
—
—
LG
NO
SH
CR
OV
CL
DATA LENGTH
OFFSET + 4
RX DATA BUFFER POINTER
OFFSET + 6
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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| MC68040FE25A | 功能描述:微處理器 - MPU 32B W/ CACHE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68040FE25V | 功能描述:微處理器 - MPU 32B W/ CACHE MMU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68040FE33A | 功能描述:微處理器 - MPU 32B W/ CACHE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68040FE33V | 功能描述:微處理器 - MPU 32B W/ CACHE MMU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68040FE40A | 功能描述:微處理器 - MPU 32B W/ CACHE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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