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| 型號(hào)： | MC68360FE25V |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | QUad Integrated Communications Controller Users Manual |
| 中文描述： | 32-BIT, 25 MHz, RISC MICROCONTROLLER, CQFP240 |
| 封裝： | CERAMIC, QFP-240 |
| 文件頁(yè)數(shù)： | 27/28頁(yè) |
| 文件大小： | 159K |
| 代理商： | MC68360FE25V |
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MOTOROLA
MC68360 USER’S MANUAL ERRATA
27
5. Phase Jitter Performance.
The phase jitter of the PLL is defined as the variations in the skew between the rising edges
of EXTAL and CLKO1/2 for a given device in specific temperature, voltage, input frequency,
MF, and capacitive load on CLKO1/2. These variations are result of the PLL locking
mechanism. For input frequencies greater than 10MHZ and MF<=4, this jitter is less than +/
-1.0ns. Otherwise, this jitter is not guaranteed. However, for MF<10 and input frequencies
greater than 10MHz this jitter is less than +/-2.6ns.
6. Frequency Jitter Performance.
The frequency jitter of the PLL is defined as the variation of the frequency of CLKO1/2. For
small MF (MF<10) this jitter is smaller than 0.5%. For mid-range MF (10 < MF < 500) this
jitter is between 0.5% and ~2%. For large MF (MF > 500), the frequency jitter is 2-3%.
7. Input (EXTAL) Jitter Requirements.
The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency
at EXTAL is slow (i.e. it does not jump between the min and max values in one cycle) or the
frequency of the jitter is fast (i.e. it does not stay at an extreme value for a long time) then
the allowed jitter can be 2%. The phase and frequency jitter performance results are only
valid if the input jitter is less than the prescribed values.
8. K-Factor for A.C. Specification.
The following numbers should be used to estimate derating of load capacitance.
a. K-factor for decreasing load (less then 100pf) = 0.2 [ns/10Pf]
b. K-factor for increasing load (more then 100pf) = 0.6 [ns/10pf]
9. Low Frequency Oscillator Use.
The output of the Voltage Controlled Oscillator (VCO) shown in Figure 6-5 is twice the
resultant clock of the PLL. Thus, a 25 MHz clock yields a VCO output of 50 MHz. If a user
wishes to use a low speed clock, the output of VCO must be at least 10 MHz. If the MODCK
values of 11 or 10 are used, the default multiplication factor is 401. Therefore, the lowest
speed input clock that can be used is 12 kHz. However, the system can operate with even
slower system frequency (slower than 12 kHz). This can be achieved by dividing down the
clock using the CDVCR. If the user chooses this method, the following conditions apply:
(a). EXTAL and QUICC internal clock phases will not be synchronized.
(b). CLKO1 will not be a 50% duty cycle.
(c). CLKO2 output (if enabled) will be the frequency of PLL's output before division.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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