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參數資料
| 型號： | MC74F257AD |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Processor Supervisory Circuits 5-SOT-23 -40 to 85 |
| 中文描述： | F/FAST SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數： | 2/3頁 |
| 文件大小： | 61K |
| 代理商： | MC74F257AD |
4-128
FAST AND LS TTL DATA
MC74F257A
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
74
4.5
5.0
5.5
V
TA
Operating Ambient Temperature Range
74
0
25
70
°
C
IOH
Output Current — High
74
–3.0
mA
IOL
Output Current — Low
74
24
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage
VIK
Input Clamp Diode Voltage
–1.2
V
IIN = –18 mA
VCC = MIN
VOH
Output HIGH Voltage
74
2.4
3.3
V
IOH = –3.0 mA
VCC = 4.50 V
74
2.7
3.3
V
IOH = –3.0 mA
VCC = 4.75 V
VOL
Output LOW Voltage
0.35
0.5
V
IOL = 24 mA
VCC = MIN
IOZH
Output OFF Current — HIGH
50
μ
A
VOUT = 2.7 V
VCC = MAX
IOZL
Output OFF Current — LOW
–50
μ
A
VOUT = 0.5 V
VCC = MAX
IIH
Input HIGH Current
20
μ
A
VIN = 2.7 V
VCC = MAX
100
VIN = 7.0 V
IIL
Input LOW Current
–0.6
mA
VIN = 0.5 V
VCC = MAX
IOS
Output Short Circuit Current (Note 2)
–60
–150
mA
VOUT = 0 V
VCC = MAX
ICCH
9.0
15
S, I1x = 4.5 V
OE, I0x = GND
ICCL
Power Supply Current
14.5
22
mA
I1x = 4.5 V
VCC = MAX
OE, I0x, S = GND
ICCZ
15
23
S, I0x = GND
OE, I1x = 4.5 V
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, nor for more than 1 second.
FUNCTIONAL DESCRIPTION
The F257A is a quad 2-input multiplexer with 3-state out-
puts. It selects four bits of data from two sources under control
of a Common Data Select input. When the Select input is
LOW, the I0x inputs are selected and when Select is HIGH, the
I1x inputs are selected. The data on the selected inputs ap-
pears at the outputs in true (non-inverted) form. The device is
the logic implementation of a 4-pole, 2-position switch where
the position of the switch is determined by the logic levels sup-
plied to the Select input. The logic equations for the outputs are
shown below:
Za = OE
(I
1a
S + I0a
S)
Zb = OE
(I1b
S + I0b
S)
Zc = OE
(I1c
S + I0c
S)
Zd = OE
(I1d
S + I0d
S)
When the Output Enable input (OE) is HIGH, the outputs are
forced to a high impedance OFF state. If the outputs are tied
together, all but one device must be in the high impedance
state to avoid high currents that would exceed the maximum
ratings. Designers should ensure the Output Enable signals to
3-state devices whose outputs are tied together are designed
so there is no overlap.
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