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參數資料
| 型號： | NCT7491RQR2G |
| 廠商： | ON Semiconductor |
| 文件頁數： | 55/80頁 |
| 文件大小： | 844K |
| 描述： | IC REMOTE THERMAL MONITOR 24QSOP |
| 標準包裝： | 2,500 |
| 系列： | * |
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NCT7491
http://onsemi.com
55
Table 69. TEMPERATURE LIMIT REGISTERS (Note 22)
Register Address
R/W
Description (Note 23)
PowerOn Default
0x4E
R/W
Remote 1 temperature low limit.
0x81
0x4F
R/W
Remote 1 temperature high limit.
0x7F
0x50
R/W
Local temperature low limit.
0x81
0x51
R/W
Local temperature high limit.
0x7F
0x52
R/W
Remote 2 temperature low limit.
0x81
0x53
R/W
Remote 2 temperature high limit.
0x7F
22.Exceeding any of these temperature limits by 1癈 causes the appropriate status bit to be set in the interrupt status register. Setting the
Configuration Register 1 lock bit has no effect on these registers.
23.High limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low limits: An interrupt is generated when a value
is equal to or below its low limit (d comparison).
Table 70. FAN TACHOMETER LIMIT REGISTERS (Note 24)
Register Address
R/W
Description
PowerOn Default
0x54
R/W
TACH1 minimum low byte.
0xFF
0x55
R/W
TACH1 minimum high byte
0xFF
0x56
R/W
TACH2 minimum low byte.
0xFF
0x57
R/W
TACH2 minimum high byte.
0xFF
0x58
R/W
TACH3 minimum low byte.
0xFF
0x59
R/W
TACH3 minimum high byte.
0xFF
0x5A
R/W
TACH4 minimum low byte.
0xFF
0x5B
R/W
TACH4 minimum high byte.
0xFF
24.Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set
in Interrupt Status Register 2 to indicate the fan failure.
Table 71. PWM CONFIGURATION REGISTERS
Register Address
R/W
Description
PowerOn Default
0x5C
R/W
PWM1 configuration.
0x02
0x5D
R/W
PWM2 configuration.
0x02
0x5E
R/W
PWM3 configuration.
0x02
Bit
Name
R/W
Description
<2:0>
SPIN
R/W
These bits control the startup timeout for PWMx. The PWM output stays high until two valid TACH
rising edges are seen from the fan. If there is not a valid TACH signal during the fan TACH meas-
urement directly after the fan startup timeout period, then the TACH measurement reads 0xFFFF
and Status Register 2 reflects the fan fault. If the TACH minimum high and low bytes contain
0xFFFF or 0x0000, then the Status Register 2 bit is not set, even if the fan has not started.
000 = No startup timeout
001 = 100 ms
010 = 250 ms (default)
011 = 400 ms
100 = 667 ms
101 = 1 sec
110 = 2 sec
111 = 4 sec
<3>
Reserved
<4>
INV
R/W
This bit inverts the PWM output. The default is 0, which corresponds to a logic high output for
100% duty cycle. Setting this bit to 1 inverts the PWM output, so 100% duty cycle corresponds to
a logic low output.
<7:5>
Reserved
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