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參數(shù)資料
| 型號(hào)： | S25FL004D0LMFI011 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| 中文描述： | 4M X 1 FLASH 3V PROM, PDSO8 |
| 封裝： | 0.208 INCH, LEAD FREE, SOP-8 |
| 文件頁數(shù)： | 13/36頁 |
| 文件大小： | 724K |
| 代理商： | S25FL004D0LMFI011 |
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S25FL Family (Serial Peripheral Interface) S25FL004D
S25FL004D_00A0 June 28, 2004
Ad va n c e
In f o rm a t i o n
the Status Register may be read to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle,
and is 0 when it is completed. At some unspecified time before the cycle is com-
pleted, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) instruction applied to a page that is protected by the Block
Protect (BP2, BP1, BP0) bits (see Table 1) is not executed.
Figure 11. Page Program (PP) Instruction Sequence
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector.
Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been de-
coded, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low,
followed by the instruction code, and three address bytes on Serial Data Input
(SI). Any address inside the Sector (see Table 1) is a valid address for the Sector
Erase (SE) instruction. Chip Select (CS#) must be driven Low for the entire du-
ration of the sequence.
The instruction sequence is shown in Figure 12.
Chip Select (CS#) must be driven High after the eighth bit of the last address byte
has been latched in, otherwise the Sector Erase (SE) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Sector Erase cycle
(whose duration is tSE) is initiated. While the Sector Erase cycle is in progress,
the Status Register may be read to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle,
0
34
33
32
31
30
29
28
10
9
8
7
6
5
4
3
2
1
35 36 37 38 39
46
45
44
43
42
41
40
47 48 49 50 51 52 53 54 55
2073
2072
2076
2075
2074
2079
2078
2077
23 22 21
3
21
07
6
5
43
2
1
0
Data Byte 1
24-Bit Address
Instruction
Data Byte 2
Data Byte 3
Data Byte 256
MSB
SCK
SI
SCK
SI
7
65
4
3
2
1
0
76
54
32
1
0
7
6
5
432
10
CS#
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| S25FL004D0LMFI013 | 4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004D0LNFI011 | 4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004D0LNFI013 | 4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S25FL004D0LMFI013 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004D0LNAI011 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004D0LNAI013 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004D0LNFI011 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004D0LNFI013 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
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