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參數(shù)資料
| 型號(hào)： | S25FL004D |
| 廠商： | Spansion Inc. |
| 英文描述： | 4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| 中文描述： | 4兆位的CMOS閃存3.0伏，50赫茲的SPI總線接口 |
| 文件頁數(shù)： | 11/36頁 |
| 文件大小： | 724K |
| 代理商： | S25FL004D |
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June 28, 2004 S25FL004D_00A0
S25FL Family (Serial Peripheral Interface) S25FL004D
19
Ad va nc e
In forma t i o n
address, are shifted out on Serial Data Output (SO), each bit being shifted out,
at a maximum frequency FSCK, during the falling edge of Serial Clock (SCK).
The instruction sequence is shown in Figure 10. The first byte addressed can be
at any location. The address is automatically incremented to the next higher ad-
dress after each byte of data is shifted out. The whole memory can, therefore, be
read with a single (FAST_READ) instruction. When the highest address is
reached, the address counter rolls over to 00000h, allowing the read sequence to
be continued indefinitely.
The (FAST_READ) instruction is terminated by driving Chip Select (CS#) High.
Chip Select (CS#) can be driven High at any time during data output. Any
(FAST_READ) instruction, while an Erase, Program or Write cycle is in progress,
is rejected without having any effects on the cycle that is in progress.
Figure 10. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed. After the Write Enable (WREN)
instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low,
followed by the instruction code, three address bytes and at least one data byte
on Serial Data Input (SI). Chip Select (CS#) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 11.
If more than 256 bytes are sent to the device, the addressing will wrap to the
beginning of the same page, previously latched data are discarded and the last
256 data bytes are guaranteed to be programmed correctly within the same
page. If fewer than 256 Data bytes are sent to device, they are correctly pro-
grammed at the requested addresses without having any effects on the other
bytes of the same page.
Chip Select (CS#) must be driven High after the eighth bit of the last data byte
has been latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Page Program cycle
(whose duration is tPP) is initiated. While the Page Program cycle is in progress,
CS#
SCK
SI
SO
Instruction
24-Bit
Address
Dummy Byte
High Impedance
DATA OUT 1
DATA OUT 2
MSB
01
2
34
56
7
8
9
10
28 29 30
31 32 33
34 35 36 37 38
39
40 41
42 43 44 45
46
47
23 22 21
3
2
1
0
7
65
4
3
2
1
0
7
6
5
4
3
21
0
7
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| S25FL004D0FMFI | 制造商:Spansion 功能描述: |
| S25FL004D0LMAI011 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004D0LMAI013 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004D0LMFI011 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004D0LMFI013 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
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