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參數資料
型號: S25FL004D
廠商: Spansion Inc.
英文描述: 4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface
中文描述: 4兆位的CMOS閃存3.0伏,50赫茲的SPI總線接口
文件頁數: 19/36頁
文件大小: 724K
代理商: S25FL004D
26
S25FL Family (Serial Peripheral Interface) S25FL004D
S25FL004D_00A0 June 28, 2004
Ad va n c e
In f o rm a t i o n
Power-up and Power-down
The device must not be selected at power-up or power-down (that is, CS# must
follow the voltage applied on VCC) until VCC reaches the correct value as follows:
VCC (min) at power-up, and then for a further delay of tPU (as described in
VSS at power-down
A simple pull-up resistor on Chip Select (CS#) can usually be used to insure safe
and proper power-up and power-down.
The device ignores all instructions until a time delay of tPU (as described in Table
5) has elapsed after the moment that VCC rises above the minimum VCC thresh-
old. However, correct operation of the device is not guaranteed if by this time VCC
is still below VCC (min). No Write Status Register, Program or Erase instructions
should be sent until tPU after VCC reaches the minimum VCC threshold (See Figure
At power-up, the device is in Standby mode (not Deep Power Down mode) and
the WEL bit is reset.
During Power-down or voltage drops, the power down must drop below the VCC
(low) for a period of minimum tPD for the device to initialize correctly on power
up. (See Figure 18).
Normal precautions must be taken for supply rail decoupling to stabilize the VCC
feed. Each device in a system should have the VCC rail decoupled by a suitable
capacitor close to the package pins (this capacitor is generally of the order of 0.1
F).
At power-down, when VCC drops from the operating voltage to below the mini-
mum VCC threshold, all operations are disabled and the device does not respond
to any instructions. (The designer needs to be aware that if a power-down occurs
while a Write, Program or Erase cycle is in progress, data corruption can result.)
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