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參數資料
| 型號： | S25FL004D |
| 廠商： | Spansion Inc. |
| 英文描述： | 4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| 中文描述： | 4兆位的CMOS閃存3.0伏，50赫茲的SPI總線接口 |
| 文件頁數： | 5/36頁 |
| 文件大小： | 724K |
| 代理商： | S25FL004D |
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June 28, 2004 S25FL004D_00A0
S25FL Family (Serial Peripheral Interface) S25FL004D
13
Ad va nc e
In forma t i o n
Instructions
All instructions, addresses, and data are shifted in and out of the device, starting
with the most significant bit. Serial Data Input (SI) is sampled on the first rising
edge of Serial Clock (SCK) after Chip Select (CS#) is driven Low. Then, the one-
byte instruction code must be shifted in to the device, most significant bit first,
on Serial Data Input (SI), each bit being latched on the rising edges of Serial
Clock (SCK). The instruction set is listed in Table 3.
Every instruction sequence starts with a one-byte instruction code. Depending on
the instruction, this might be followed by address bytes, or by data bytes, or by
both or none. Chip Select (CS#) must be driven High after the last bit of the in-
struction sequence has been shifted in.
In the case of a Read Data Bytes (READ), Read Status Register (RDSR), Fast Read
(FAST_READ) or Release from Deep Power Down and Read Electronic Signature
(RES) instruction, the shifted-in instruction sequence is followed by a data-out
sequence. Chip Select (CS#) can be driven High after any bit of the data-out se-
quence is being shifted out to terminate the transaction.
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write
Status Register (WRSR), Write Enable (WREN), or Write Disable (WRDI) instruc-
tion, Chip Select (CS#) must be driven High exactly at a byte boundary,
otherwise the instruction is rejected, and is not executed. That is, Chip Select
(CS#) must driven High when the number of clock pulses after Chip Select (CS#)
being driven Low is an exact multiple of eight.
All attempts to access the memory array during a Write Status Register cycle,
Program cycle or Erase cycle are ignored, and the internal Write Status Register
cycle, Program cycle or Erase cycle continues unaffected
Table 3. Instruction Set.
Instruction
Description
One-Byte Instruction
Code
Address
Bytes
Dummy
Byte
Data Bytes
Status Register Operations
WREN
Write Enable
06H (0000 0110)
0
WRDI
Write Disable
04H (0000 0100)
0
RDSR
Read from Status Register
05H (0000 0101)
0
1 to Infinity
WRSR
Write to Status Register
01H (0000 0001)
0
1
Read Operations
READ
Read Data Bytes
03H (0000 0011)
3
0
1 to Infinity
FAST_READ
Read Data Bytes at Higher Speed
0BH (0000 1011)
3
1
1 to Infinity
Erase Operations
SE
Sector Erase
D8H (1101 1000)
3
0
BE
Bulk (Chip) Erase
C7H (1100 0111)
0
Program Operations
PP
Page Program
02H (0000 0010)
3
0
1 to 256
Deep Power Down Savings Mode Operations
DP
Deep Power Down
B9H (1011 1001)
0
RES
Release from Deep Power Down
ABH (1010 1011)
0
Release from Deep Power Down and
Read Electronic Signature
ABH (1010 1011)
0
3
1 to Infinity
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相關代理商/技術參數 |
參數描述 |
|---|---|
| S25FL004D0FMFI | 制造商:Spansion 功能描述: |
| S25FL004D0LMAI011 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004D0LMAI013 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004D0LMFI011 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
| S25FL004D0LMFI013 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Interface |
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