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參數資料
| 型號： | S25FL064A0LNAI00 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 64M X 1 FLASH 3V PROM, PDSO16 |
| 封裝： | 0.300 INCH, PLASTIC, MS-013AA, SOP-16 |
| 文件頁數： | 15/36頁 |
| 文件大小： | 1495K |
| 代理商： | S25FL064A0LNAI00 |
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June 29, 2007 S25FL064A_00_C3
S25FL064A
23
Data
She e t
9.8
Page Program (PP)
The Page Program (PP) command changes specified bytes in the memory array (from 1 to 0 only). A WREN
command is required prior to writing the PP command.
The host system must drive CS# low, and then write the PP command, three address bytes, and at least one
data byte on SI. CS# must be driven low for the entire duration of the PP sequence. The command sequence
is shown in Figure 9.8 and Table 9.4 on page 28.
The device programs only the last 256 data bytes sent to the device. If the number of data bytes exceeds this
limit, the bytes sent before the last 256 bytes are discarded, and the device begins programming the last 256
bytes sent at the starting address of the specified page. This may result in data being programmed into
different addresses within the same page than expected. If fewer than 256 data bytes are sent to device, they
are correctly programmed at the requested addresses.
The host system must drive CS# high after the device has latched the 8th bit of the data byte, otherwise the
device does not execute the PP command. The PP operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of tPP. The Status Register may
be read to check the value of the Write In Progress (WIP) bit while the PP operation is in progress. The WIP
bit is 1 during the PP operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device does not execute a Page Program (PP) command that specifies a page that is protected by the
Block Protect bits (BP2:BP0) (see Table 7.1 on page 13).
Figure 9.8 Page Program (PP) Command Sequence
0
34
33
32
31
30
29
28
10
9
8
7
6
5
4
3
2
1
35 36 37 38
39
46
45
44
43
42
41
40
47 48 49 50
51 52 53 54
55
207
3
2072
2076
2075
2074
2079
207
8
2077
23 22 21
3
21
07
6
5
4
3
2
1
0
Data Byte 1
24-Bit Address
Command
Data Byte 2
Data Byte 3
Data Byte 256
MSB
SCK
SI
SCK
SI
7
65
4
3
2
1
0
76
54
3
21
0
7
6
5
4
3
21
0
CS#
Mode 0
Mode 3
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相關代理商/技術參數 |
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| S25FL064K | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:64-Mbit CMOS 3.0 Volt Flash Memory with 80-MHz SPI (Serial Peripheral Interface) Multi I/O Bus |
| S25FL064K0SMFI010 | 功能描述:閃存 IC 64MBIT CMOS 3V FL MEMORY 80-MHZ SPI RoHS:否 制造商:ON Semiconductor 數據總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| S25FL064K0SMFI011 | 功能描述:閃存 IC 64MBIT CMOS 3V FL MEMORY 80-MHZ SPI RoHS:否 制造商:ON Semiconductor 數據總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| S25FL064K0SMFI013 | 制造商:Spansion 功能描述:FLASH SERL-SPI 3V/3.3V 64MBIT - Bulk |
| S25FL064LABBHI020 | 功能描述:IC FLASH NOR 24FBGA 制造商:cypress semiconductor corp 系列:FL-L 包裝:托盤 零件狀態:在售 存儲器類型:非易失 存儲器格式:閃存 技術:FLASH - NOR 存儲容量:64Mb （8M x 8） 時鐘頻率:108MHz 寫周期時間 - 字，頁:- 存儲器接口:SPI - 四 I/O， QPI 電壓 - 電源:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C（TA） 安裝類型:表面貼裝 封裝/外殼:24-TBGA 供應商器件封裝:24-BGA（6x8） 標準包裝:338 |
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