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參數資料
型號: S25FL064A0LNAI00
廠商: SPANSION LLC
元件分類: PROM
英文描述: 64M X 1 FLASH 3V PROM, PDSO16
封裝: 0.300 INCH, PLASTIC, MS-013AA, SOP-16
文件頁數: 4/36頁
文件大小: 1495K
代理商: S25FL064A0LNAI00
June 29, 2007 S25FL064A_00_C3
S25FL064A
13
Data
She e t
7.6
Data Protection Modes
Spansion SPI Flash memory devices provide the following data protection methods:
The Write Enable (WREN) command: Must be written prior to any command that modifies data. The
WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up
or after the device completes the following commands:
– Page Program (PP)
– Sector Erase (SE)
– Bulk Erase (BE)
– Write Disable (WRDI)
– Write Status Register (WRSR)
Software Protected Mode (SPM): The Block Protect (BP2, BP1, BP0) bits define the section of the
memory array that can be read but not programmed or erased. Table 7.1 shows the sizes and address
ranges of protected areas that are defined by Status Register bits BP2:BP0.
Hardware Protected Mode (HPM): The Write Protect (W#) input and the Status Register Write Disable
(SRWD) bit together provide write protection.
Clock Pulse Count: The device verifies that all program, erase, and Write Status Register commands
consist of a clock pulse count that is a multiple of eight before executing them.
Table 7.1 S25FL064A Protected Area Sizes
Status Register
Block Protect Bits
Memory Array
Protected
Portion of
Total Memory
Area
BP2
BP1
BP0
Protected
Address Range
Protected Sectors
Unprotected
Address Range
Unprotected
Sectors
0
None
(0)
000000h–7FFFFFh
SA127:SA0
0
1
7E0000h–7FFFFFh
(2) SA127:SA126
000000h–7DFFFFh
SA125:SA0
1/64
0
1
0
7C0000h–7FFFFFh
(4) SA127:SA124
000000h–7BFFFFh
SA123:SA0
1/32
0
1
780000h–7FFFFFh
(8) SA127:SA120
000000h–77FFFFh
SA119:SA0
1/16
1
0
700000h–7FFFFFh
(16) SA127:SA112
000000h–6FFFFFh
SA111:SA0
1/8
1
0
1
600000h–7FFFFFh
(32) SA127:SA96
000000h–5FFFFFh
SA95:SA0
1/4
1
0
400000h–7FFFFFh
(64) SA127:SA64
000000h–3FFFFFh
SA63:SA0
1/2
1
000000h–7FFFFFh
(128) SA127:SA0
None
All
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