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參數資料
| 型號： | S29AL032D90TFI043 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 32 Megabit CMOS 3.0 Volt-only Flash Memory |
| 中文描述： | 2M X 16 FLASH 3V PROM, 90 ns, PDSO48 |
| 封裝： | LEAD FREE, MO-142DD, TSOP-48 |
| 文件頁數： | 6/67頁 |
| 文件大小： | 1708K |
| 代理商： | S29AL032D90TFI043 |
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12
S29AL032D
S29AL032D_00_A8 November 2, 2006
Da ta
Sh e e t
6.2
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
7.
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location.
The register is composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the device. Table 7.1 lists the device bus operations, the
inputs and control levels they require, and the resulting output. The following subsections describe each of
these operations in further detail.
Legend
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes
1. When the ACC pin is at VHH, the device enters the accelerated program mode. See
2. Addresses are A20:A0 in word mode (BYTE# = VIH), A20:A-1 in byte mode (BYTE# = VIL).
3. The sector protect and sector unprotect functions may also be implemented via programming equipment.
4. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were
last protected or unprotected. If WP#/ACC = VHH, all sectors are unprotected.
5. DIN or DOUT as required by command sequence, data polling, or sector protection algorithm.
6. Models 03, 04 only
7.1
Word/Byte Configuration (Models 03, 04 Only)
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word
configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15–DQ0 are active and
controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used
as an input for the LSB (A-1) address function.
Table 7.1 S29AL032D Device Bus Operations
Operation
CE#
OE#
WE#
RESET#
WP#(Note 6)/ACC
Addresses
DQ0–
DQ7
DQ8–DQ15 (Note 6)
BYTE#
= VIH
BYTE# = VIL
Read
L
H
L/H
AIN
DOUT
DQ8–DQ14 =
High-Z, DQ15 =
A-1
Write (Note 1)
LH
L
H
AIN
Accelerated Program
LH
L
H
VHH
AIN
Standby
VCC ±
0.3 V
XX
VCC ±
0.3 V
H
X
High-Z
Output Disable
L
H
L/H
X
High-Z
Reset
X
L
L/H
X
High-Z
Sector Protect (Note 3)
LH
L
VID
L/H
SA, A6 = L,
A1 = H, A0 = L
XX
Sector Unprotect
LH
L
VID
SA, A6 = H,
A1 = H, A0 = L
XX
Temporary Sector
Unprotect
XX
X
VID
AIN
High-Z
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