- 您現在的位置：買賣IC網 > PDF目錄192295 > S29CD032J1MQFN133 (SPANSION LLC) 1M X 32 FLASH 2.7V PROM, 54 ns, PQFP80 PDF資料下載
參數資料
| 型號： | S29CD032J1MQFN133 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 1M X 32 FLASH 2.7V PROM, 54 ns, PQFP80 |
| 封裝： | LEAD FREE, PLASTIC, MO-108CB-1, QFP-80 |
| 文件頁數： | 16/78頁 |
| 文件大小： | 1825K |
| 代理商： | S29CD032J1MQFN133 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁
September 27, 2006 S29CD-J_CL-J_00_B1
S29CD-J & S29CL-J Flash Family
21
Pr el im i n a r y
8.2
Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation, data
is read from one memory location at a time. Addresses are presented to the device in random
order, and the propagation delay through the device causes the data on its outputs to arrive
asynchronously with the address on its inputs.
The internal state machine is set for asynchronously reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory content occurs
during the power transition. No command is necessary in this mode to obtain array data. Stan-
dard microprocessor read cycles that assert valid addresses on the device address inputs
produce valid data on the device data outputs. The device remains enabled for read access until
the command register contents are altered.
The device has two control functions which must be satisfied in order to obtain data at the out-
puts. CE# is the power control and should be used for device selection (CE# must be set to VIL
to read data). OE# is the output control and should be used to gate data to the output pins if
the device is selected (OE# must be set to VIL in order to read data). WE# should remain at VIH
(when reading data).
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The
chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data
at the output pins. The output enable access time (tOE) is the delay from the falling edge of OE#
to valid data at the output pins (assuming the addresses have been stable for at least a period
diagram of an asynchronous read operation.
Note: Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required.
Figure 8.1 Asynchronous Read Operation
Refer to Asynchronous Operations on page 56 for timing specifications and to Figure 18.2, Con-
ventional Read Operations Timings, on page 56 for another timing diagram. ICC1 in the DC
Characteristics table represents the active current specification for reading array data.
D0
D1
D2
D3
CE#
CLK
ADV#
Addresses
Data
OE#
WE#
IND/WAIT#
VIH
Float
VOH
Address 0
Address 1
Address 2
Address 3
Float
相關PDF資料 |
PDF描述 |
|---|---|
| S29CL016J0JQFI100 | 512K X 32 FLASH 3.3V PROM, 54 ns, PQFP80 |
| S29CL016J0MFAI113 | 512K X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
| S29CL016J0PQFI102 | 512K X 32 FLASH 3.3V PROM, 54 ns, PQFP80 |
| S29CL016J0MFAM100 | 512K X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
| S29CL016J0PFFM102 | 512K X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| S29CL016J0JQFM030 | 制造商:Spansion 功能描述:FLASH PARALLEL 3.3V 16MBIT 512KX32 54NS 80PQFP - Trays |
| S29CL016J0JQFM030P | 制造商:Spansion 功能描述:AUTO 3.3V 512KX32 FLASH - Trays |
| S29CL016J0JQFM030U | 制造商:Spansion 功能描述:32M (4MX8/2MX16) 3V REG, MIRRORBIT, TOP, FBGA48, IND - Trays |
| S29CL016J0JQFM03U | 制造商:Spansion 功能描述:32M (4MX8/2MX16) 3V REG, MIRRORBIT, TOP, FBGA48, IND - Trays |
| S29CL016J0MQFM030 | 制造商:Spansion 功能描述: |
發布緊急采購，3分鐘左右您將得到回復。