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參數資料
| 型號： | TC55VBM416AFTN55 |
| 廠商： | Toshiba Corporation |
| 英文描述： | CABLE 30 COND RIBBON WHT 100FT |
| 中文描述： | 1,048,576字由16位/ 2097152字的8位全的CMOS靜態RAM |
| 文件頁數： | 1/14頁 |
| 文件大小： | 204K |
| 代理商： | TC55VBM416AFTN55 |
TC55VBM416AFTN55
2002-08-29 1/14
TENTATIVE
1,048,576-WORD BY 16-BIT/2,097,152-WORD BY 8-BIT FULL CMOS STATIC RAM
DESCRIPTION
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
The TC55VBM416AFTN is a 16,777,216-bit static random access memory (SRAM) organized as 1,048,576 words
by 16 bits/2,097,152 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device
operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provides both high speed and low
power at an operating current of 3 mA/MHz and a minimum cycle time of 55 ns. It is automatically placed in
low-power mode at 0.9
μ
A standby current (at V
DD
=
3 V, Ta
=
25°C, typical) when chip enable (CE1) is asserted
high or (CE2) is asserted low. There are three control inputs. CE1 and CE2 are used to select the device and for
data retention control, and output enable (OE ) provides fast memory access. Data byte control pin (LB, UB )
provides lower and upper byte access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. And, with a guaranteed operating extreme
temperature range of
40° to 85°C, the TC55VBM416AFTN can be used in environments exhibiting extreme
temperature conditions. The TC55VBM416AFTN is available in a plastic 48-pin thin-small-outline package
(TSOP).
FEATURES
Low-power dissipation
Operating: 9 mW/MHz (typical)
Single power supply voltage of 2.3 to 3.6 V
Power down features usingCE1 and CE2
Data retention supply voltage of 1.5 to 3.6 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of
40° to 85°C
Standby Current (maximum):
3.6 V
3.0 V
15
μ
A
8
μ
A
PIN ASSIGNMENT
(TOP VIEW)
PIN NAMES
48 PIN TSOP
A0~A19
A-1~A19
1
CE
, CE2
R/W
OE
LB ,
UB
I/O1~I/O16
BYTE
V
DD
GND
NC
OP*
Address Inputs (Word Mode)
Address Inputs (Byte Mode)
Chip Enable
Read/Write Control
Output Enable
Data Byte Control
Data Inputs/Outputs
Byte (
×
8 mode) Enable
Power
Ground
No Connection
Option
*: OP pin must be open or connected to GND.
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
R/W
CE2
OP
UB
LB
A18
Pin No.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin Name
A17
A7
A6
A5
A4
A3
A2
A1
A0
1
CE
GND
OE
I/O1
I/O9
I/O2 I/O10
Pin No.
33
34
35
36
37
38
I/O5 I/O13 I/O6 I/O14 I/O7 I/O15 I/O8 I/O16
39
40
41
42
43
44
45
46
47
48
Pin Name
I/O3 I/O11 I/O4 I/O12 V
DD
/A-1
GND
BYTE
A16
Access Times (maximum):
Access Time
55 ns
1
CE
Access Time
55 ns
CE2 Access Time
55 ns
OE
Access Time
30 ns
Package:
TSOP
48-P-1220-0.50
(Weight:0.51 g typ)
(Normal)
25
48
24
1
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