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參數資料
型號： TMP320C6413ZTS500
廠商： Texas Instruments, Inc.
元件分類： 數字信號處理
英文描述： Fixed-Point Digital Signal Processors
中文描述： 定點數字信號處理器
文件頁數： 57/140頁
文件大小： 1958K
代理商： TMP320C6413ZTS500
Terminal Functions
57
April 2004
Revised May 2005
SPRS247E
Table 3
9. Terminal Functions (Continued)
NAME
NO.
TYPE
IPD/
IPU
DESCRIPTION
JTAG EMULATION (CONTINUED)
Emulation pin 2. Reserved for future use, leave unconnected.
Emulation pin 3. Reserved for future use, leave unconnected.
Emulation pin 4. Reserved for future use, leave unconnected.
Emulation pin 5. Reserved for future use, leave unconnected.
Emulation pin 6. Reserved for future use, leave unconnected.
Emulation pin 7. Reserved for future use, leave unconnected.
Emulation pin 8. Reserved for future use, leave unconnected.
Emulation pin 9. Reserved for future use, leave unconnected.
Emulation pin 10. Reserved for future use, leave unconnected.
Emulation pin 11. Reserved for future use, leave unconnected.
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS
I
Device reset
I
IPD
Nonmaskable interrupt, edge-driven (rising edge)
EMU2
EMU3
EMU4
EMU5
EMU6
EMU7
EMU8
EMU9
EMU10
EMU11
R2
U2
R3
P2
R4
V2
V1
V3
W3
W2
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
RESET
NMI
C9
B9
GP0[7]/EXT_INT7
Y1
I/O/Z
IPU
General-purpose input/output (GPIO) pins (
I/O/Z
) or external interrupts (
input only
).
Th d f
l f
i GPIO
The default after reset setting is GPIO enabled as input-only.
When these pins function as External Interrupts [by selecting the corresponding
interrupt enable register bit (IER.[7:4])], they are edge-driven and the polarity can be
independently selected via the External Interrupt Polarity Register bits
(EXTPOL.[3:0]).
bl d
GP0[6]/EXT_INT6
C4
I/O/Z
IPU
p p
p
GP0[5]/EXT_INT5
B4
I/O/Z
IPU
GP0[4]/EXT_INT4
A4
I/O/Z
IPU
HD15/GP0[15]
HD14/GP0[14]
HD13/GP0[13
]
HD12/GP0[12]
HD11/GP0[11]
HD10/GP0[10]
HD9/GP0[9]
HD8/GP0[8]
GP0[3]
CLKOUT6/GP0[2]
§
CLKOUT4/GP0[1]
§
GP0[0]
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
Y12
AA12
AB13
Y14
AB14
AA15
Y16
AB16
B13
B3
A2
D13
I/O/Z
IPU
Host-port data pins (
I/O/Z
) [default] or General-purpose input/output (GP0) [15:8] pins
(
I/O/Z
)
p p
GP0 [3:0] pins (
I/O/Z
)
Clock output at 1/6 of the device speed (
O/Z
) [default] or this pin can be programmed as
GP0 2 i (
a GP0 2 pin (
I/O/Z
).
Clock output at 1/4 of the device speed (
O/Z
) [default] or this pin can be programmed as
a GP0 1 pin (
I/O/Z
).
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
IPU
IPU
IPD
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