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參數資料
| 型號： | TMP320C6413ZTS500 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processors |
| 中文描述： | 定點數字信號處理器 |
| 文件頁數： | 90/140頁 |
| 文件大小： | 1958K |
| 代理商： | TMP320C6413ZTS500 |
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Device Electrical Specifications
90
April 2004
Revised May 2005
SPRS247E
5.3
Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Case Temperature (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
DV
DD
= MIN,
DV
DD
= MIN,
V
I
= V
SS
to DV
DD
no opposing internal
resistor
MIN
2.4
TYP
MAX
UNIT
V
V
V
OH
V
OL
High-level output voltage
Low-level output voltage
I
OH
= MAX
I
OL
= MAX
0.4
±
10
uA
I
I
Input current
V
I
= V
SS
to DV
DD
opposing internal
pullup resistor
50
100
150
uA
V
I
= V
SS
to DV
DD
opposing internal
pulldown resistor
150
100
50
uA
I
OH
High level output current
High-level output current
EMIF, CLKOUT4, CLKOUT6, EMUx
Timer, TDO, GPIO, McBSP, HPI
EMIF, CLKOUT4, CLKOUT6, EMUx
Timer, TDO, GPIO, McBSP, HPI
SCL1, SDA1, SCL0, and SDA0
V
O
= DV
DD
or 0 V
CV
DD
= 1.2 V, CPU clock = 500 MHz
CV
DD
= 1.2 V, CPU clock = 400 MHz
DV
DD
= 3.3 V, CPU clock = 500 MHz
DV
DD
= 3.3 V, CPU clock = 400 MHz
16
8
16
mA
mA
mA
mA
mA
uA
mA
mA
mA
mA
pF
pF
I
OL
Low-level output current
Low level output current
8
3
I
OZ
Off-state output current
±
10
I
CDD
Core supply current
§
568
465
140
132
I
DDD
I/O supply current
§
C
i
C
o
For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
§
Measured with average activity (50% high/50% low power) at 25
°
C case temperature and 100-MHz EMIF for -500 and -400 speeds. This model
represents a device performing high-DSP-activity operations 50% of the time, and the remainder performing low-DSP-activity operations. The
high/low-DSP-activity models are defined as follows:
High-DSP-Activity Model:
CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;
L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
Low-DSP-Activity Model:
CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles;
L2/EMIF EDMA: None]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the
TMS320C6410/13 Power
Consumption Summary
application report (literature number SPRAA59).
Input capacitance
Output capacitance
10
10
5.4
Recommended Clock and Control Signal Transition Behavior
All clocks and control signals
must
transition between V
IH
and V
IL
(or between V
IL
and V
IH
) in a monotonic
manner.
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