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參數資料
| 型號： | TMP320C6413ZTSA400 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | Fixed-Point Digital Signal Processors |
| 中文描述： | 定點數字信號處理器 |
| 文件頁數： | 56/140頁 |
| 文件大小： | 1958K |
| 代理商： | TMP320C6413ZTSA400 |
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Terminal Functions
56
April 2004
Revised May 2005
SPRS247E
Table 3
9. Terminal Functions
SIGNAL
NAME
TYPE
IPD/
IPU
DESCRIPTION
NO.
CLOCK/PLL CONFIGURATION
Clock Input. This clock is the input to the on-chip PLL.
Clock output at 1/4 of the device speed (
O/Z
) [default] or this pin can be programmed as
a GP0 1 pin (
I/O/Z
).
CLKIN
A12
I
IPD
CLKOUT4/GP0[1]
§
A2
I/O/Z
IPU
CLKOUT6/GP0[2]
§
B3
I/O/Z
IPU
Clock output at 1/6 of the device speed (
O/Z
) [default] or this pin can be programmed as
a GP0 2 pin (
I/O/Z
).
CLKINSEL
A11
I
IPU
CLKIN select. Selects whether the PLL input clock is CLKIN [pin high] or directly from
the crystal oscillator (OSCIN and OSCOUT) [pin low].
For proper device operation, this pin
must
be used in conjunction with the OSC_DIS
pin.
CLKMODE3
CLKMODE2
CLKMODE1
CLKMODE0
PLLV
OSCIN
OSCOUT
C11
B10
A13
C13
C12
A6
A7
I
I
I
I
IPD
IPD
IPD
IPD
Clock mode selects
Selects whether the CPU clock frequency = input clock frequency x1 (Bypass), x5,
x6 x7 x8 x9 x10 x11 x12 x16 x18 x19 x20 x21 x22 or x24
x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x22, or x24.
For more details on the CLKMODE pins and the PLL multiply factors, see the Clock
PLL section of this data sheet.
PLL voltage supply
Crystal oscillator Input (XI)
Crystal oscillator output (XO)
Power for crystal oscillator (1.2 V),
Do not
connect to board power 1.4 V; for optimum
performance, connected internally. If CLKIN is used instead of the oscillator, then this
pin can be left open or connected to CV
DD
.
Ground for crystal oscillator,
Do not
connect to board ground; for optimum
performance, connected internally. If CLKIN is used instead of the oscillator, then this
pin can be left open or connected to V
SS
.
Oscillator disable select.
For proper device operation, this pin
must
follow the CLKINSEL pin operation.
0
OSC enabled; CLKINSEL
must
be 0
1
OSC disabled (default); CLKINSEL
must
be 1
JTAG EMULATION
JTAG test-port mode select
JTAG test-port data out
JTAG test-port data in
JTAG test-port clock
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG
compatibility statement portion of this data sheet.
Emulation pin 0
#
Emulation pin 1
#
A
I
O
—
—
OSCV
DD
B6
S
—
OSCV
SS
C6
GND
—
OSC_DIS
B7
I
IPU
TMS
TDO
TDI
TCK
U3
T4
T1
T2
I
IPU
IPU
IPU
IPU
O/Z
I
I
TRST
U1
I
IPD
EMU0
EMU1
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
PLLV is not part of external voltage supply. See the Clock PLL and Oscillator section for information on how to connect this pin.
#
The EMU0 and EMU1 pins are internally pulled up with 30-k
resistors; therefore, for emulation and normal operation, no external
pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-k
resistor.
R1
T3
I/O/Z
I/O/Z
IPU
IPU
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