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參數資料
型號： TMP320C6413ZTSA400
廠商： Texas Instruments, Inc.
元件分類： 數字信號處理
英文描述： Fixed-Point Digital Signal Processors
中文描述： 定點數字信號處理器
文件頁數： 74/140頁
文件大小： 1958K
代理商： TMP320C6413ZTSA400
Clock PLL and Oscillator
74
April 2004
Revised May 2005
SPRS247E
Table 4
2. TMS320C6410 PLL Multiply Factor Options, Clock Frequency Ranges,
and Typical Lock Time for
400 Devices
GTS and ZTS PACKAGES
23 x 23 mm BGA
CLKMODE[3:0]
CLKMODE
(PLL MULTIPLY FACTORS)
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
RANGE
(MHz)
12
100
140
400
140
400
140
400
140
400
140
400
140
400
140
400
144
400
192
400
216
400
228
400
240
400
252
400
264
400
288
400
OSCIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
RANGE
(MHz)
12
30
140
150
140
180
140
210
140
240
140
270
140
300
140
330
144
360
192
400
216
400
228
400
240
400
252
400
264
400
288
400
TYPICAL
LOCK TIME
(
μ
s)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Bypass (x1)
x5
x6
x7
x8
x9
x10
x11
x12
x16
x18
x19
x20
x21
x22
x24
12
100
28
80
23
67
20
57
17
50
15
44
14
40
12
36
12
33
12
25
12
22
12
21
12
20
12
19
12
18
12
17
12
30
28
30
23
30
20
30
17
30
15
30
14
30
12
30
12
30
12
25
12
22
12
21
12
20
12
19
12
18
12
17
N/A
75
Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the C6413/C6410 device to one of the valid PLL
multiply clock modes (x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x22, or x24). With internal pulldown resistors on the CLKMODE
pins (CLKMODE3, CLKMODE2, CLKMODE1, CLKMODE0), the default clock mode is x1 (bypass).
Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if
the typical lock time is specified as 100
μ
s, the maximum value may be as long as 250
μ
s.
For the lowest jitter on the oscillator circuit, it is recommended that a pair of 470-pF capacitors be connected
between isolated (not directly connected to the board supply) OSCV
DD
and OSCV
SS
pins. This helps to cancel
out switching noise from other circuits on the DSP device.
Table 4
3 shows a recommended crystal and tank circuit values for the C6413/C6410 PLL circuitry.
Table 4
3. Crystal and Tank Circuit Recommendations
Components
RECOMMENDED PART NUMBERS or VALUES
MANUFACTURER
24 576 MHz
24.576 MHz
1AS245766AHA (SMD-49)
1AF245766AAA (AT-49)
1AS225796AG (SMD-49)
1AF225796A (AT-49)
1 M
0
Crystal
KDS
Diashinku Corp.
22 5792 MHz
22.5792 MHz
R
B
R
S
C7
C8
—
—
8 pF
—
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