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參數資料
型號： TMP320C6413ZTSA400
廠商： Texas Instruments, Inc.
元件分類： 數字信號處理
英文描述： Fixed-Point Digital Signal Processors
中文描述： 定點數字信號處理器
文件頁數： 95/140頁
文件大小： 1958K
代理商： TMP320C6413ZTSA400
Input and Output Clocks
95
April 2004
Revised May 2005
SPRS247E
Table 7
5. Timing Requirements for AECLKIN for EMIFA
§
(see Figure 7
4)
NO.
400
500
UNIT
MIN
6
2.7
2.7
MAX
16P
1
2
3
4
t
c(EKI)
t
w(EKIH)
t
w(EKIL)
t
t(EKI)
t
J(EKI)
Cycle time, AECLKIN
Pulse duration, AECLKIN high
Pulse duration, AECLKIN low
Transition time, AECLKIN
ns
ns
ns
ns
3
5
Period jitter, AECLKIN
0.02E
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
The reference points for the rise and fall transitions are measured at V
IL
MAX and V
IH
MIN.
§
E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
Minimum AECLKIN cycle times
must
be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times are based
on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. 100-MHz operation is achievable
if the requirements of the EMIF Device Speed section are met.
AECLKIN
2
3
4
4
5
1
Figure 7
4. AECLKIN Timing for EMIFA
Table 7
6. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the
EMIFA Module
§#||
(see Figure 7
5)
NO.
PARAMETER
400
500
UNIT
MIN
MAX
E + 0.7
EH + 0.7
EL + 0.7
1
2
3
4
5
6
t
c(EKO1)
t
w(EKO1H)
t
w(EKO1L)
t
t(EKO1)
t
d(EKIH-EKO1H)
t
d(EKIL-EKO1L)
Cycle time, AECLKOUT1
Pulse duration, AECLKOUT1 high
Pulse duration, AECLKOUT1 low
Transition time, AECLKOUT1
Delay time, AECLKIN high to AECLKOUT1 high
Delay time, AECLKIN low to AECLKOUT1 low
E
0.7
EH
0.7
EL
0.7
ns
ns
ns
ns
ns
ns
1
8
8
1
1
§
E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns.
#
The reference points for the rise and fall transitions are measured at V
OL
MAX and V
OH
MIN.
||
EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.
5
6
2
3
AECLKIN
AECLKOUT1
4
4
1
Figure 7
5. AECLKOUT1 Timing for the EMIFA Module
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