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參數(shù)資料
型號: TMX320C6413ZTSA400
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Fixed-Point Digital Signal Processors
中文描述: 定點數(shù)字信號處理器
文件頁數(shù): 79/140頁
文件大小: 1958K
代理商: TMX320C6413ZTSA400
General-Purpose Input/Output (GPIO)
79
April 2004
Revised May 2005
SPRS247E
Figure 4
3 is a block diagram of the I2C0 and I2C1 modules.
Clock
Prescale
I2CPSCx
Peripheral Clock
(CPU/4)
I2CCLKHx
Generator
Bit Clock
I2CCLKLx
Noise
Filter
SCL
I2CXSRx
I2CDXRx
Transmit
Transmit
Shift
Transmit
Buffer
I2CDRRx
Shift
I2CRSRx
Receive
Buffer
Receive
Receive
Filter
SDA
I2C Data
Noise
I2COARx
I2CSARx
Slave
Address
Control
Address
Own
I2CMDRx
I2CCNTx
Mode
Data
Count
Source
Interrupt
Interrupt
Status
I2CISRCx
I2CSTRx
Enable
Interrupt
I2CIERx
Interrupt/DMA
I2Cx Module
NOTE A: Shading denotes control/status registers.
I2C Clock
I2CEMDRx
I2CPFUNCx
I2CPDIRx
I2CPDINx
I2CPDOUTx
I2CPDSETx
I2CPDCLRx
GPIO Control
Function
Pin
Direction
Pin
In
Pin Data
Out
Pin Data
Set
Pin Data
Clear
Pin Data
Extended
Mode
Figure 4
3. I2Cx Module Block Diagram
4.5
General-Purpose Input/Output (GPIO)
On the C6413/C6410 device the GPIO peripheral pins GP0[15:9] are muxed with the HPI peripheral pins
HD[15:9], respectively. By default, the HPI peripheral pin functions are enabled [TOUT0/HPI_EN pin internall
pulled low]. For more detailed information on device/peripheral configuration and the C6413/C6410 device
pin muxing, see the Device Configurations section of this data sheet.
To use the GP0[15:0] software-configurable GPIO pins, the GPxEN bits in the GP Enable (GPEN) Register
and the GPxDIR bits in the GP Direction (GPDIR) Register must be properly configured.
GPxEN =
1
GP[x] pin is enabled
GPxDIR =
0
GP[x] pin is an input
GPxDIR =
1
GP[x] pin is an output
where “x” represents one of the 15 through 0 GPIO pins
Figure 4
4 shows the GPIO enable bits in the GPEN register for the C6413/C6410 device. To use any of the
GPx pins as general-purpose input/output functions, the corresponding GPxEN bit must be set to “1”
(enabled). Default values are device-specific, so refer to Figure 4
4 for the C6413/C6410 default
configuration.
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