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參數(shù)資料
型號： TMX320C6413ZTSA500
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Fixed-Point Digital Signal Processors
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 110/140頁
文件大小： 1958K
代理商： TMX320C6413ZTSA500
HOLD/HOLDA Timing
110
April 2004
Revised May 2005
SPRS247E
7.5
HOLD/HOLDA Timing
Table 7
14. Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module
(see Figure 7
20)
NO.
400
500
UNIT
MIN
MAX
3
t
h(HOLDAL-HOLDL)
Hold time, HOLD low after HOLDA low
E
ns
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
Table 7
15. Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA
Cycles for EMIFA Module
§
(see Figure 7
20)
NO.
PARAMETER
400
500
UNIT
MIN
2E
MAX
1
2
4
5
6
7
t
d(HOLDL-EMHZ)
t
d(EMHZ-HOLDAL)
t
d(HOLDH-EMLZ)
t
d(EMLZ-HOLDAH)
t
d(HOLDL-EKOHZ)
t
d(HOLDH-EKOLZ)
Delay time, HOLD low to EMIFA Bus high impedance
Delay time, EMIF Bus high impedance to HOLDA low
Delay time, HOLD high to EMIF Bus low impedance
Delay time, EMIFA Bus low impedance to HOLDA high
Delay time, HOLD low to AECLKOUTx high impedance
Delay time, HOLD high to AECLKOUTx low impedance
ns
ns
ns
ns
ns
ns
0
2E
7E
2E
2E
0
2E
2E
7E
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
EMIFA Bus consists of: ACE[3:0], ABE[3:0], AED[31:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and
AAWE/ASDWE/ASWE
,
ASDCKE, ASOE3, and APDT.
§
The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 7
20.
All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
HOLD
HOLDA
EMIF Bus
DSP Owns Bus
External Requestor
Owns Bus
DSP Owns Bus
C6413/C6410
C6413/C6410
1
3
2
5
4
AECLKOUTx
(EKxHZ = 0)
AECLKOUTx
(EKxHZ = 1)
6
7
EMIFA Bus consists of: ACE[3:0], ABE[3:0], AED[31:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and
AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT.
The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 7
20.
Figure 7
20. HOLD/HOLDA Timing for EMIFA
相關(guān)PDF資料
PDF描述
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