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參數資料
型號： TMX320C6413ZTSA500
廠商： Texas Instruments, Inc.
元件分類： 數字信號處理
英文描述： Fixed-Point Digital Signal Processors
中文描述： 定點數字信號處理器
文件頁數： 118/140頁
文件大小： 1958K
代理商： TMX320C6413ZTSA500
Inter-Integrated Circuits (I2C) Timing
118
April 2004
Revised May 2005
SPRS247E
7.10
Inter-Integrated Circuits (I2C) Timing
Table 7
22. Timing Requirements for I2C Timings
(see Figure 7
26)
400
500
NO.
STANDARD
MODE
FAST
MODE
UNIT
MIN
MAX
MIN
2.5
MAX
1
t
c(SCL)
Cycle time, SCL
Setup time, SCL high before SDA low (for a repeated START
condition)
10
μ
s
2
t
su(SCLH-SDAL)
4.7
0.6
μ
s
3
t
h(SCLL-SDAL)
Hold time, SCL low after SDA low (for a START and a repeated
START condition)
4
0.6
μ
s
4
5
6
7
8
9
10
11
12
13
14
15
t
w(SCLL)
t
w(SCLH)
t
su(SDAV-SDLH)
t
h(SDA-SDLL)
t
w(SDAH)
t
r(SDA)
t
r(SCL)
t
f(SDA)
t
f(SCL)
t
su(SCLH-SDAH)
t
w(SP)
C
b#
Pulse duration, SCL low
Pulse duration, SCL high
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low (For I
2
C bus
devices)
Pulse duration, SDA high between STOP and START conditions
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
Setup time, SCL high before SDA high (for STOP condition)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
4.7
1.3
0.6
μ
s
μ
s
ns
μ
s
μ
s
ns
ns
ns
ns
μ
s
ns
pF
4
250
0
§
4.7
100
0
§
1.3
0.9
1000
1000
300
300
20 + 0.1C
b#
20 + 0.1C
b#
20 + 0.1C
b#
20 + 0.1C
b#
300
300
300
300
4
0.6
0
50
400
400
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
A Fast-mode I
2
C-bus
device can be used in a Standard-mode I
2
C-bus
system, but the requirement t
su(SDA
SCLH)
≥
250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line t
r
max + t
su(SDA
SCLH)
= 1000 + 250 = 1250 ns (according to the Standard-mode
I
2
C-Bus Specification) before the SCL line is released.
§
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IHmin
of the SCL signal) to bridge the undefined
region of the falling edge of SCL.
The maximum t
h(SDA
SCLL)
has only to be met if the device does not stretch the low period [t
w(SCLL)
] of the SCL signal.
#
C
b
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
10
8
4
3
7
12
5
6
14
2
3
13
Stop
Start
Repeated
Start
Stop
SDA
SCL
1
11
9
Figure 7
26. I2C Receive Timings
相關PDF資料
PDF描述
TMX320C6413ZTS400 Fixed-Point Digital Signal Processors
TMP320C6413ZTS400 Fixed-Point Digital Signal Processors
TMX320C6413ZTS500 Fixed-Point Digital Signal Processors
TMP320C6413ZTS500 Fixed-Point Digital Signal Processors
TMX320C6413ZTSA400 Fixed-Point Digital Signal Processors
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