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參數(shù)資料
| 型號(hào)： | TMX320C6413ZTSA500 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Fixed-Point Digital Signal Processors |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 120/140頁(yè) |
| 文件大小： | 1958K |
| 代理商： | TMX320C6413ZTSA500 |
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Host-Port Interface (HPI) Timing
120
April 2004
Revised May 2005
SPRS247E
7.11
Host-Port Interface (HPI) Timing
Table 7
24. Timing Requirements for Host-Port Interface Cycles
(see Figure 7
28 through Figure 7
35)
NO.
400
500
UNIT
MIN
5
2.4
4P
4P
5
2
5
2.8
MAX
1
2
3
4
10
11
12
13
t
su(SELV-HSTBL)
t
h(HSTBL-SELV)
t
w(HSTBL)
t
w(HSTBH)
t
su(SELV-HASL)
t
h(HASL-SELV)
t
su(HDV-HSTBH)
t
h(HSTBH-HDV)
Setup time, select signals
§
valid before HSTROBE low
Hold time, select signals
§
valid after HSTROBE low
Pulse duration, HSTROBE low
Pulse duration, HSTROBE high between consecutive accesses
Setup time, select signals
§
valid before HAS low
Hold time, select signals
§
valid after HAS low
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not complete
properly.
ns
ns
ns
ns
ns
ns
ns
ns
14
t
h(HRDYL-HSTBL)
2
ns
18
19
t
su(HASL-HSTBL)
t
h(HSTBL-HASL)
Setup time, HAS low before HSTROBE low
Hold time, HAS low after HSTROBE low
2
ns
ns
2.1
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
§
Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.
Select the parameter value of 4P or 12.5 ns, whichever is larger.
Table 7
25. Switching Characteristics Over Recommended Operating Conditions During Host-Port
Interface Cycles
(see Figure 7
28 through Figure 7
35)
NO.
PARAMETER
400
500
UNIT
MIN
1.3
MAX
4P + 8
6
t
d(HSTBL-HRDYH)
t
d(HSTBL-HDLZ)
t
d(HDV-HRDYL)
t
oh(HSTBH-HDV)
t
d(HSTBH-HDHZ)
Delay time, HSTROBE low to HRDY high
#
ns
7
Delay time, HSTROBE low to HD low impedance for an HPI read
2
ns
8
9
15
Delay time, HD valid to HRDY low
Output hold time, HD valid after HSTROBE high
Delay time, HSTROBE high to HD high impedance
3
1.5
ns
ns
ns
12
16
t
d(HSTBL-HDV)
Delay time, HSTROBE low to HD valid (HPI16 mode, 2nd half-word only)
2P + 8 or
0P + 8
||
ns
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
#
This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word transfer (HPI16)
on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until
the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is
full.
||
If preceeding HSTROBE high pulse width > 6P, then this parameter value can be 0P + 8 ns.
相關(guān)PDF資料 |
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| TMX320C6413ZTS400 | Fixed-Point Digital Signal Processors |
| TMP320C6413ZTS400 | Fixed-Point Digital Signal Processors |
| TMX320C6413ZTS500 | Fixed-Point Digital Signal Processors |
| TMP320C6413ZTS500 | Fixed-Point Digital Signal Processors |
| TMX320C6413ZTSA400 | Fixed-Point Digital Signal Processors |
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