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參數(shù)資料
型號: TMX320C6413ZTSA500
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Fixed-Point Digital Signal Processors
中文描述: 定點數(shù)字信號處理器
文件頁數(shù): 82/140頁
文件大小: 1958K
代理商: TMX320C6413ZTSA500
Power-Down Modes Logic
82
April 2004
Revised May 2005
SPRS247E
4.6
Power-Down Modes Logic
Figure 4
6 shows the power-down mode logic on the C6413/C6410.
PWRD
Internal Clock Tree
CPU
IFR
IER
CSR
PD1
PD2
Power-
Down
Logic
Clock
PLL
CLKIN
RESET
CLKOUT6
PD3
Internal
Peripherals
CLKOUT4
Clock
Distribution
and Dividers
External input clocks, with the exception of CLKIN, are
not
gated by the power-down mode logic.
TMS320C6413/C6410
Figure 4
6. Power-Down Mode Logic
Note: to further save power, the PERCFG register can be used to disable unused peripherals. For more
detailed information on disabling peripherals using the PERCFG register, see the
Device Configurations
section of this data sheet.
4.6.1
Triggering, Wake-up, and Effects
The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15
10)
of the control status register (CSR). The PWRD field of the CSR is shown in Figure 4
7 and described in
Table 4
4. When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should
be used when writing to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the
TMS320C6000 CPU and Instruction Set Reference Guide
(literature number SPRU189).
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