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參數資料
型號： TMX320F2810PBKA
廠商： Texas Instruments, Inc.
元件分類： 數字信號處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數字信號處理器
文件頁數： 37/103頁
文件大小： 1341K
代理商： TMX320F2810PBKA
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
37
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
vector table mapping (continued)
Reset
(Power-on Reset or
Warm Reset)
PIE Disabled (ENPIE = 0)
VMAP = 1
OBJMODE = 0
AMODE = 0
M0M1MAP = 1
XMP/MC
input signal
= 0
(F2812 Only)
Reset Vector Fetched
from XINTF Vector Map
Reset Vector Fetched
from Boot ROM
Branch into Bootloader
routines depending on
the state of GPIO Pins
Using
Peripheral
Interrupts
VMAP = 1
(F2812 Only)
Vectors (except for reset) will be
fetched from XINTF Vector Map
§
Vectors (except for reset)
will be Fetched From
BROM Vector Map
§
MP/MC
status bit =
0
Vectors (except for reset)
will be
fetched from PIE Vector Map
§
No
Yes
No
Yes
No
Yes
No
Yes
Vectors (except for reset) will be
fetched from M0 Vector Map
§
The XMP/MC input signal is tied low internally on the F2810.
The compatibility operating mode of the F2810 and F2812 is determined by a combination of the OBJMODE and AMODE bits in Status
Register 1 (ST1):
Operating Mode
C28x Mode
C2xLP Source-Compatible
C27x Object-Compatible
OBJMODE
1
1
0
AMODE
0
1
0 (Default at reset)
§
The reset vector is always fetched from either the BROM or XINTF vector map depending on the XMP/MC input signal.
The state of the XMP/MC signal is latched into the MP/MC bit at reset, it can then be modified by software.
Recommended Flow for F2810/F2812 Applications
Used for Test Purposes Only
User Code Initializes:
OBJMODE and AMODE State
PIE Enable (ENPIE = 1)
PIE Vector Table
PIEIERx Registers
CPU IER Register and INTM
User Code Initializes:
OBJMODE and AMODE State
CPU IER Register and INTM
VMAP State
MP/MC Status Bit
Figure 7. Reset Flow Diagram
P
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TMP320F2810PBKA DIGITAL SIGNAL PROCESSORS
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