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參數資料
| 型號： | TMX320F2810PBKA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 數字信號處理器 |
| 文件頁數： | 47/103頁 |
| 文件大小： | 1341K |
| 代理商： | TMX320F2810PBKA |
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
47
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
system control (continued)
The system control and status register contains the watchdog override bit and the watchdog interrupt
enable/disable bit. Table 33 describes the bit functions of the SCSR register.
Table 33. SCSR Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
0
WDOVERRIDE
R/W=1
1
If this bit is set to 1, the user is allowed to change the state of the Watchdog
disable (WDDIS) bit in the Watchdog Control (WDCR) register (refer to
Watchdog Block section of this data sheet). If the WDOVERRIDE bit is
cleared, by writing a 1 the WDDIS bit cannot be modified by the user.
Writing a 0 will have no effect. If this bit is cleared, then it will remain in this
state until a reset occurs. The current state of this bit is readable by the user.
1
WDENINT
R/W
0
If this bit is set to 1, the watchdog reset (WDRST) output signal is disabled
and the watchdog interrupt (WDINT) output signal is enabled. If this bit is
zero, then the WDRST output signal is enabled and the WDINT output
signal is disabled. This is the default state on reset (XRS).
15:2
reserved
R=0
0:0
The HISPCP and LOSPCP registers are used to configure the high- and low-speed peripheral clocks,
respectively. See Table 34 for the HISPCP bit definitions and Table 35 for the LOSPCP bit definitions.
Table 34. HISPCP Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
2:0
HSPCLK
R/W
0,0,1
These bits configure the high-speed peripheral clock (HSPCLK) rate
relative to SYSCLKOUT:
000
HSPCLK = SYSCLKOUT / 1
001
HSPCLK = SYSCLKOUT / 2
010
HSPCLK = SYSCLKOUT / 4
011
HSPCLK = SYSCLKOUT / 6
100
HSPCLK = SYSCLKOUT / 8
101
HSPCLK = SYSCLKOUT / 10
110
HSPCLK = SYSCLKOUT / 12
111
HSPCLK = SYSCLKOUT / 14
HSPCLK =
SYSCLKOUT / (HSPCLK x 2)
SYSCLKOUT if HISPCP value is zero
=
15:3
reserved
R=0
0:0
P
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